Title: Optimized ASIP Synthesis from Architecture Description Language Models, Author: Oliver Schliebusch
Title: Practical Formal Methods for Hardware Design, Author: Carlos Delgado Kloos
Title: Writing Testbenches using SystemVerilog, Author: Janick Bergeron
Title: Fundamentals and Standards in Hardware Description Languages, Author: Jean Mermet
Title: The e Hardware Verification Language, Author: Sasan Iman
Title: Electronic Chips & Systems Design Languages, Author: Jean Mermet
Title: Optimized ASIP Synthesis from Architecture Description Language Models, Author: Oliver Schliebusch
Title: Higher-Level Hardware Synthesis, Author: Richard Sharp
Title: Electronic Chips & Systems Design Languages, Author: Jean Mermet
Title: System on Chip Design Languages: Extended papers: best of FDL'01 and HDLCon'01 / Edition 1, Author: Anne Mignotte
Title: CTL for Test Information of Digital ICs, Author: Rohit Kapur
Title: Writing Testbenches: Functional Verification of HDL Models / Edition 2, Author: Janick Bergeron
Title: Architecture Exploration for Embedded Processors with LISA, Author: Andreas Hoffmann
Title: System Specification & Design Languages: Best of FDL'02, Author: Eugenio Villar
Title: Writing Testbenches using SystemVerilog, Author: Janick Bergeron
Title: High-Level Synthesis: from Algorithm to Digital Circuit, Author: Philippe Coussy
Title: Architecture Exploration for Embedded Processors with LISA, Author: Andreas Hoffmann
Title: Hardware Description Languages and their Applications: Specification, modelling, verification and synthesis of microelectronic systems, Author: Carlos Delgado Kloos
Title: High-Level System Modeling: Specification Languages, Author: Jean-Michel Bergï
Title: High-Level Synthesis: from Algorithm to Digital Circuit, Author: Philippe Coussy

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