Title: Higher-Level Hardware Synthesis, Author: Richard Sharp
Title: Modeling with an Analog Hardware Description Language, Author: H. Alan Mantooth
Title: High-Level Synthesis: from Algorithm to Digital Circuit, Author: Philippe Coussy
Title: Writing Testbenches: Functional Verification of HDL Models, Author: Janick Bergeron
Title: System-on-Chip Methodologies & Design Languages, Author: Peter J. Ashenden
Title: Architecture Exploration for Embedded Processors with LISA, Author: Andreas Hoffmann
Title: High-Level Synthesis: from Algorithm to Digital Circuit, Author: Philippe Coussy
Title: Fundamentals and Standards in Hardware Description Languages, Author: Jean Mermet
Title: Optimized ASIP Synthesis from Architecture Description Language Models, Author: Oliver Schliebusch
Title: System Specification & Design Languages: Best of FDL'02, Author: Eugenio Villar
Title: High-Level System Modeling: Specification Languages, Author: Jean-Michel Bergé
Title: Electronic Chips & Systems Design Languages, Author: Jean Mermet
Title: Analog and Mixed-Signal Hardware Description Language, Author: A. Vachoux
Title: Writing Testbenches using SystemVerilog, Author: Janick Bergeron
Title: Writing Testbenches: Functional Verification of HDL Models, Author: Janick Bergeron
Title: System on Chip Design Languages: Extended papers: best of FDL'01 and HDLCon'01, Author: Anne Mignotte
Title: Architecture Exploration for Embedded Processors with LISA, Author: Andreas Hoffmann
Title: The e Hardware Verification Language, Author: Sasan Iman
Title: Writing Testbenches using SystemVerilog, Author: Janick Bergeron
Title: Advances in Design and Specification Languages for SoCs: Selected Contributions from FDL'04, Author: Pierre Boulet

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