21st IEEE VLSI Test Symposium

Overview

Papers from a spring 2003 symposium describe innovations in the testing of integrated circuits and systems. Organization is in sections on areas such as built-in self-test, silicon proven IP cores, test compaction, testing buses and on-chip interconnect, test challenges in nanometer technologies, and advanced test generation and fault simulation. Other themes include testing high-speed I/Os, test data compression, memory testing, power consumption and test, testing core-based SoCs, and layout driven design for ...
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Overview

Papers from a spring 2003 symposium describe innovations in the testing of integrated circuits and systems. Organization is in sections on areas such as built-in self-test, silicon proven IP cores, test compaction, testing buses and on-chip interconnect, test challenges in nanometer technologies, and advanced test generation and fault simulation. Other themes include testing high-speed I/Os, test data compression, memory testing, power consumption and test, testing core-based SoCs, and layout driven design for test and manufacturability. There is no subject index. Annotation (c)2003 Book News, Inc., Portland, OR
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Product Details

  • ISBN-13: 9780769519241
  • Publisher: Wiley, John & Sons, Incorporated
  • Publication date: 1/28/2003
  • Pages: 492

Table of Contents

Foreword
Organizing committee
Steering committee
Program committee
Reviewers
Acknowledgements
Test technology technical council
Test technology educational program : overview of tutorials
A DIFT success story ... 3
Building yields into systems-on-chips for nanometer technology 4
A reconfigurable shared scan-in architecture 9
Test data compression and test time reduction of longest-path-per-gate tests based on Illinois scan architecture 15
Transition test generation using replicate-and-reduce transform for scan-based designs 22
Use of multiple I[subscript DDQ] test metrics for outlier identification 31
Effectiveness comparisons of outlier screening methods for frequency dependent defects on complex ASICs 39
Effectiveness of I-V testing in comparison to I[subscript DDQ] tests 47
High speed ring generators and compactors of test data 57
Built-in reseeding for serial BIST 63
BIST reseeding with very few seeds 69
Ultra low cost analog BIST using spectral analysis 77
DSP-based statistical self test of on-chip converters 83
High-coverage analog wafer-probe test design and co-optimization with assembled-package test to minimize overall test cost 89
Analysis and design of optimal combinational compactors 101
Application of Saluja-Karpovsky compactors to test responses with many unknowns 107
Decompression hardware determination for test volume and time reduction through unified test pattern compaction and compression 113
Eliminating non-determinism during test of high-speed source synchronous differential buses 121
The impact of NoC reuse on the testing of core-based systems 128
Automatic configuration generation for EPGA interconnect testing 134
Threshold voltage mismatch ([Delta]V[subscript Tu]) fault modeling 145
Test generation for maximizing ground bounce considering circuit delay 151
Testing SoC interconnects for signal integrity using boundary scan 158
On maximizing the fault coverage for a given test length limit in a synchronous sequential circuit 173
An efficient test relaxation technique for synchronous sequential circuits 179
Path-delay fault simulation for circuits with large numbers of paths for very large test sets 186
1149.4 based on-line quiescent state monitoring technique 197
Measurement of phase and frequency variations in radio-frequency signals 203
An analog checker with dynamically adjustable error threshold for fully differential circuits 209
Test data compression using dictionaries with fixed-length indices 219
Deterministic test vector decompression in software using linear operations 225
Efficient seed utilization for reseeding based compression 232
Detecting intra-word faults in word-oriented memories 241
Test and diagnosis of word-oriented multiport memories 248
Generating complete and optimal march tests for linked faults in memories 254
Energy-efficient logic BIST based on state correlation analysis 267
Power constrained test scheduling with dynamically varied TAM 273
Development of energy consumption ratio test 279
Design for consecutive transparency of cores in system-on-a-chip 287
An embedded autonomous scan-based results analyzer (EARA) for SoC cores 293
Design and optimization of multi-level TAM architectures for hierarchical SoCs 299
Embedded tutorial : test consideration for nanometer scale CMOS circuits 313
Test resource partitioning and optimization for SoC designs 319
SoC test scheduling using simulated annealing 325
Layered approach to designing system test interfaces 331
Diagnosis of delay defects using statistical timing models 339
Improving diagnostic resolution of delay faults using path delay fault model 345
Concurrent execution of diagnostic fault simulation and equivalence identification during diagnostic test generation 351
BIST-aided scan test - a new method for test cost reduction 359
Built-in TPG with designed phaseshifts 365
A test interface for built-in test of non-isolated scanned cores 371
A circuit level fault model for resistive opens and bridges 379
Analyzing crosstalk in the presence or weak bridge defects 385
Efficient implication - based untestable bridge fault identifier 393
Testable design and testing of micro-electro-fluidic arrays 403
Fault testing for reversible circuits 410
Design for self-checking and self-timed datapath 417
Author index 431
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