21st International Conference on Computer Design : ICCD 2003

Overview

Seventy-eight papers from the October 2003 conference present new developments in computer system design, logic and circuits, tools and methodology, verification and testing, and processor architecture. Many of the researchers address the challenges of energy efficiency, power management, hardware/software co-design, and reliability increasingly required for automotive controls, mobile communications, and personal entertainment systems. Topics include verification of time circuits with failure directed ...
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Overview

Seventy-eight papers from the October 2003 conference present new developments in computer system design, logic and circuits, tools and methodology, verification and testing, and processor architecture. Many of the researchers address the challenges of energy efficiency, power management, hardware/software co-design, and reliability increasingly required for automotive controls, mobile communications, and personal entertainment systems. Topics include verification of time circuits with failure directed abstractions, a method for fast noise estimation based on net segmentation, static test compaction for multiple full-scan circuits, exploiting micro-architectural redundancy for defect tolerance, and structural detection of symmetries in Boolean functions. No subject index. Annotation ©2003 Book News, Inc., Portland, OR
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Product Details

  • ISBN-13: 9780769520254
  • Publisher: Wiley, John & Sons, Incorporated
  • Publication date: 1/28/2003
  • Pages: 586

Table of Contents

Welcome
Organizing Committee
Program Committee
Additional Reviewers
High-Speed Link Design, Then and Now
Terascale Computing and BlueGene
Advanced EDA Tools for High-Performance Design
Energy Efficient Asymmetrically Ported Register Files 2
Power Efficient Data Cache Designs 8
On Reducing Register Pressure and Energy in Multiple-Banked Register Files 14
Low Power Multiplication Algorithm for Switching Activity Reduction through Operand Decomposition 21
Verification of Timed Circuits with Failure Directed Abstractions 28
Procedures for Identifying Untestable and Redundant Transition Faults in Synchronous Sequential Circuits 36
Event-Centric Simulation of Crosstalk Pulse Faults in Sequential Circuits 42
Specifying and Verifying Systems with Multiple Clocks 48
Enhanced QMM-BEM Solver for 3-D Finite-Domain Capacitance Extraction with Multilayered Dielectrics 58
An Improved Method for Fast Noise Estimation Based on Net Segmentation 64
Symbolic Failure Analysis of Custom Circuits due to Excessive Leakage Current 70
An Efficient Algorithm for Calculating the Worst-case Delay due to Crosstalk 76
A Compact Model for Analysis and Design of On-chip Power Network with Decoupling Capacitors 84
Precomputation-Based Guarding for Dynamic and Leakage Power Reduction 90
Charge-Recycling Voltage Domains for Energy-Efficient Low-Voltage Operation of Digital CMOS Circuits 98
Low Power Adder with Adaptive Supply Voltage 103
A Transparent Voltage Conversion Method and Its Application to a Dual-Supply-Voltage Register File 107
Detection of Biological Molecules: From Self-Assembled Films to Self-Integrated Devices 112
Design Flow Enhancements for DNA Arrays 116
Bus Architecture Synthesis for Hardware-Software Co-Design of Deep Submicron Systems on Chip 126
Dynamically Optimized Synchronous Communication for Low Power System on Chip Designs 134
Interface Synthesis Using Memory Mapping for an FPGA Platform 140
Efficient Synthesis of Networks On Chip 146
Reducing Compilation Time Overhead in Compiled Simulators 151
Profiling Interrupt Handler Performance through Kernel Instrumentation 156
Design and Performance of Compressed Interconnects for High Performance Servers 164
Routed Inter-ALU Networks for ILP Scalability and Performance 170
Automatic Generation of Critical-Path Tests for a Partial-Scan Microprocessor 180
Test Generation for Non-separable RTL Controller-datapath Circuits Using a Satisfiability Based Approach 187
Cost-Effective Graceful Degradation in Speculative Processor Subsystems: The Branch Prediction Case 194
Multiple Fault Diagnosis Using n-Detection Tests 198
A Physical Design Methodology for 1.3GHz SPARC64 Microprocessor 204
Physical Design of the "2.5D" Stacked System 211
Flow-Based Cell Moving Algorithm for Desired Cell Distribution 218
NpBench: A Benchmark Suite for Control plane and Data plane Applications for Network Processors 226
Hardware-Only Compression of Underutilized Address Buses: Design and Performance, Power, and Cost Analysis 234
Pipelined Multiplicative Division with IEEE Rounding 240
Design of Resonant Global Clock Distributions 248
Modeling and Mitigation of Jitter in Multi-Gbps Source-Synchronous I/O Links 254
A Mixed-Mode Delay-Locked Loop Architecture 261
Optimal Inductance for On-chip RLC Interconnections 264
Spec Based Flip-Flop and Buffer Insertion 270
A Microeconomic Model for Simultaneous Gate Sizing and Voltage Scaling for Power Optimization 276
A Simple Yet Effective Merging Scheme for Prescribed-Skew Clock Routing 282
Hardware-Based Pointer Data Prefetcher 290
A Dependence Driven Efficient Dispatch Scheme 299
An Efficient VLIW DSP Architecture for Baseband Processing 307
Dynamic Thread Resizing for Speculative Multithreaded Processors 313
Care Bit Density and Test Cube Clusters: Multi-Level Compression Opportunities 320
XMAX: X-Tolerant Architecture for MAXimal Test Compression 326
Test Data Compression and Compaction for Embedded Test of Nanometer Technology Designs 331
Non-Crossing OBDDs for Mapping to Regular Circuit Structures 338
Interconnect Estimation for FPGAs under Timing Driven Domains 344
ROAD: An Order-Impervious Optimal Detailed Router for FPGAs 350
Reducing dTLB Energy through Dynamic Resizing 358
Distributed Reorder Buffer Schemes for Low Power 364
Virtual Page Tag Reduction for Low-Power TLBs 371
Dynamic Cluster Resizing 375
Independent Test Sequence Compaction through Integer Programming 380
On Combining Pinpoint Test Set Relaxation and Run-Length Codes for Reducing Test Data Volume 387
Static Test Compaction for Multiple Full-Scan Circuits 393
A Method to Find Don't Care Values in Test Sequences for Sequential Circuits 397
Simplifying SoC Design with the Customizable Control Processor Platform 402
Structured ASICs: Opportunities and Challenges 404
System LSI Implementation Fabrics for the Future 410
Multiple-V[subscript dd] Scheduling/Allocation for Partitioned Floorplan 412
SCATOMi: Scheduling Driven Circuit Partitioning Algorithm for Multiple FPGAs Using Time-multiplexed, Off-chip, Multicasting Interconnection Architecture 419
A Study of Hardware Techniques that Dynamically Exploit Frequent Operands to Reduce Power Consumption in Integer Function Units 426
KnapBind: An Area-Efficient Binding Algorithm for Low-leakage Datapaths 430
A Novel Synthesis Strategy Driven by Partial Evaluation Based Circuit Reduction for Application Specific DSP Circuits 436
Power Fluctuation Minimization During Behavioral Synthesis Using ILP-Based Datapath Scheduling 441
An Energy-Aware Simulation Model and Transaction Protocol for Dynamic Workload Distribution in Mobile Ad Hoc Networks 444
CMOS High-Speed Serial I/Os - Present and Future 454
Fully Differential Receiver Chipset for 40 Gb/s Applications Using GaInAs/InP Single Heterojunction Bipolar Transistors 462
Paradigm Shift for Jitter and Noise in Design and Test>GB/s Data Communication Systems 467
Cost-Efficient Memory Architecture Design of NAND Flash Memory Embedded Systems 474
Exploiting Microarchitectural Redundancy for Defect Tolerance 481
Reducing Multimedia Decode Power Using Feedback Control 489
Structural Detection of Symmetries in Boolean Functions 498
Boolean Decomposition Based on Cyclic Chains 504
SAT-Based Algorithms for Logic Minimization 510
Low-Density Parity-Check Decoder Architecture for High Throughput Optical Fiber Channels 520
Improving Branch Prediction Accuracy in Embedded Processors in the Presence of Context Switches 526
Reducing Operand Transport Complexity of Superscalar Processors Using Distributed Register Files 532
xpipes: a Latency Insensitive Parameterized Network-on-chip Architecture for Multi-Processor SoCs 536
Aggressive Test Power Reduction through Test Stimuli Transformation 542
Power-Time Tradeoff in Test Scheduling for SoCs 548
Multiple Transition Model and Enhanced Boundary Scan Architecture to Test Interconnects for Signal Integrity 554
Author Index 561
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