Table of Contents
Acknowledgments xi
Introduction xv
Chapter 1 Programmatic and System-Level Considerations 1
1.1 Introduction: Sensors Think 1
1.2 Product Development Stages 2
1.3 Product Development Stages: Tailoring 5
1.4 Product Development: After Launch 6
1.5 Requirements 7
1.5.1 The V-Model 10
1.5.2 SensorsThink: Product Requirements 12
1.5.3 Creating Useful Requirements 13
1.5.4 Requirements: Finishing Up 16
1.6 Architectural Design 16
1.6.1 SEBoK: An Invaluable Resource 17
1.6.2 SensorsThink: Back to the Journey 20
1.6.3 Systems Engineering: An Overview 21
1.6.4 Architecting the System, Logically 23
1.6.5 Keep Things in Context (Diagrams) 24
1.6.6 Monitor Your Activity (Diagrams) 26
1.6.7 Know the Proper Sequence (Diagrams) 28
1.6.8 Architecting the System Physically 28
1.6.9 Physical Architecture: Playing with Blocks 29
1.6.10 Trace Your Steps 31
1.6.11 System Verification and Validation: Check Your Work 32
1.7 Engineering Budgets 33
1.7.1 Types of Budgets 33
1.7.2 Engineering Budgets: Some Examples 34
1.7.3 Engineering Budgets: Finishing Up 38
1.8 Interface Control Documents 38
1.8.1 Sticking Together: Signal Grouping 39
1.8.2 Playing with Legos: Connectorization 41
1.8.3 Talking Among Yourselves: Internal ICDs 42
1.9 Verification 42
1.9.1 Verifying Hardware 43
1.9.2 How Much Testing Is Enough? 43
1.9.3 Safely Navigating the World of Testing 44
1.9.4 A Deeper Dive into Derivation (of Test Cases) 45
1.10 Engineering Governance 47
1.10.1 Not Just Support for Design Reviews 48
1.10.2 Engineering Rule Sets 48
1.10.3 Compliance 49
1.10.4 Review Meetings 49
References 50
Chapter 2 Hardware Design Considerations 53
2.1 Component Selection 53
2.1.1 Key Component Identification for the SoC Platform 53
2.1.2 Key Component Selection Example: The SoC 57
2.1.3 Key Component Selection Example: Infrared Sensor 63
2.1.4 Key Component Selection: Finishing Up 65
2.2 Hardware Architecture 66
2.2.1 Hardware Architecture for the SoC Platform 66
2.2.2 Hardware Architecture: Interfaces 70
2.2.3 Hardware Architecture: Data Flows 72
2.2.4 -Hardware Architecture: Finishing Up 72
2.3 Designing the System 72
2.3.1 What to Worry About 73
2.3.2 Power Supply Analysis, Architecture, and Simulation 73
2.3.3 Processor and FPGA Pinout Assignments 74
2.3.4 System Clocking Requirements 75
2.3.5 System Reset Requirements 75
2.3.6 System Programming Scheme 75
2.3.7 Summary 76
2.3.8 Example: Zynq Power Sequence Requirements 76
2.4 Decoupling Your Components 78
2.4.1 Decoupling: By the Book 78
2.4.2 To Understand the Component, You Must Be the Component 78
2.4.3 Types of Decoupling 79
2.4.4 Example: Zynq-7000 Decoupling 80
2.4.5 Additional Thoughts: Specialized Decoupling 81
2.4.6 Additional Thoughts: Simulation 81
2.5 Connect with Your System 82
2.5.1 Contemplating Connectors 82
2.5.2 Example: System Communications 83
2.6 Extend the Life of the System: De-Rate 87
2.6.1 Why De-Rate? 87
2.6.2 What Can Be De-Rated? 87
2.6.3 Example: De-Rating the Zynq-7000 89
2.6.4 Additional Thoughts: Exceptions to the Rule 89
2.7 Test, Test, Test 90
2.7.1 Back to Basics: Pre-Power-On Checklist 90
2.7.2 Check for Signs of Life: Crawl Before Walking 93
2.7.3 Roll Up Your Sleeves and Get Ready to Run 94
2.7.4 Example: I2C Interface 95
2.7.5 Additional Thoughts 97
2.8 Integrity: Important for Electronics 97
2.8.1 Power Integrity 98
2.8.2 Signal Integrity 98
2.8.3 Digging Deeper into Power Integrity 99
2.8.4 Digging Deeper into Signal Integrity 100
2.8.5 Example: ULPI Pre-Layout Analysis 102
2.8.6 Suggested Additional Reading 104
2.9 PCB Layout: Not for the Faint of Heart 104
2.9.1 Floor Planning 106
2.9.2 Follow the Rats 108
2.9.3 Mechanical Constraints 110
2.9.4 Electrical Constraints 111
2.9.5 Stack-Up Design 113
2.9.6 Experience Matters 119
References 120
Chapter 3 FPGA Design Considerations 123
3.1 Introduction 123
3.2 FPGA Development Process 124
3.2.1 Introduction to the Target Device 126
3.2.2 FPGA Requirements 127
3.2.3 FPGA Architecture 129
3.3 Accelerating Design Using IP Libraries 130
3.4 Pin Planning and Constraints 131
3.4.1 Physical Constraints 134
3.4.2 Timing Constraints 137
3.4.3 Timing Exceptions 138
3.4.4 Physical Constraints: Placement 139
3.5 Clock Domain Crossing 140
3.6 Test Bench and Verification 143
3.6.1 What Is Verification? 143
3.6.2 Self-Checking Test Benches 144
3.6.3 Corner Cases, Boundary Conditions, and Stress Testing 145
3.6.4 Code Coverage 146
3.6.5 Test Functions and Procedures 146
3.6.6 Behavioral Models 147
3.6.7 Using Text IO Files 147
3.6.8 What Else Might We Consider? 148
3.7 Finite State Machine Design 148
3.7.1 Defining a State Machine 148
3.7.2 Algorithmic State Diagrams 149
3.7.3 Moore or Mealy: What Should I Choose? 149
3.7.4 Implementing the State Machine 150
3.7.5 State Machine Encoding 151
3.7.6 Increasing Performance of State Machines 153
3.7.7 Good Design Practices for FPGA Implementation 155
3.7.8 FUR Lepton Interface 155
3.8 Defensive State Machine Design 157
3.8.1 Detection Schemes 157
3.8.2 Hamming Schemes 159
3.8.3 Deadlock and Other Issues 160
3.8.4 Implementing Defensive State Machines in Xilinx Devices 161
3.9 How Does FPGA Do Math? 162
3.9.1 Representation of Numbers 162
3.10 Fixed Point Mathematics 163
3.10.1 Fixed-Point Rules 164
3.10.2 Overflow 166
3.10.3 Real-World Implementation 167
3.10.4 RTL Implementation 169
3.11 Polynomial Approximation 170
3.11.1 The Challenge with Some Algorithms 171
3.11.2 Capitalize on FPGA Resources 172
3.11.3 Multiple Trend Lines Selected by Input Value 173
3.12 The CORDIC Algorithm 173
3.13 Convergence 176
3.14 Where Are These Used? 176
3.15 Modeling in Excel 176
3.16 Implementing the CORDIC 177
3.17 Digital Filter Design and Implementation 179
3.17.1 Filter Types and Topologies 179
3.17.2 Frequency Response 181
3.17.3 Impulse Response 181
3.17.4 Step Response 182
3.17.5 Windowing the Filter 182
3.18 Fast Fourier Transforms 184
3.18.1 Time or Frequency Domain? 184
3.19 How Do We Get There? 184
3.19.1 Where Do We Use These? 186
3.19.2 FPGA-Based Implementation 186
3.19.3 Higher-Speed Sampling 188
3.20 Working with ADC and DAC 189
3.20.1 ADC and DAC Key Parameters 189
3.20.2 The Frequency Spectrum 191
3.20.3 Communication 191
3.20.4 DAC Filtering 192
3.20.5 In-System Test 192
3.21 High-Level Synthesis 193
Chapter 4 When Reliability Counts 199
4.1 Introduction to Reliability 199
4.2 Mathematical Interpretation of System Reliability 201
4.2.1 The Bathtub Curve 202
4.2.2 Failure Rate (A) 202
4.2.3 Early Life Failure Rate 204
4.2.4 Key Terms 205
4.2.5 Repairable and Nonrepairable Systems 206
4.2.6 MTTF, MTBF, and MTTR 206
4.2.7 Maintainability 208
4.2.8 Availability 209
4.3 Calculating System Reliability 210
4.3.1 Scenario 1: All Critical Components Connected in Series 212
4.3.2 Scenario 2: All Critical Components Connected in Parallel 215
4.3.3 Scenario 3: All Critical Components Are Connected in Series-Parallel Configuration 216
4.4 Faults, Errors, and Failure 216
4.4.1 Classification of Faults 218
4.4.2 Fault Prevention Versus Fault Tolerance: Which One Can Address System Failure Better? 219
4.5 Fault Tolerance Techniques 221
4.5.1 Redundancy Technique for Hardware Fault Tolerance' 223
4.5.2 Software Fault Tolerance 224
4.6 Worst-Case Circuit Analysis 227
4.6.1 Sources of Variation 230
4.6.2 Numerical Analysis Using SPICE Modeling 233
Selected Bibliography 240
About the Authors 241
Index 243
