A Pipelined Multi-Core Machine with Operating System Support: Hardware Implementation and Correctness Proof

by Petro Lutsyk, Jonas Oberhauser, Wolfgang J. Paul

Overview

This work is building on results from the book named “A Pipelined Multi-core MIPS Machine: Hardware Implementation and Correctness” by M. Kovalev, S.M. Müller, and W.J. Paul, published as LNCS 9000 in 2014.

It presents, at the gate level, construction and correctness proof of a multi-core machine with pipelined processors and extensive operating system support with the following features:

• MIPS instruction set architecture (ISA) for application and for system programming

• cache coherent memory system

• store buffers in front of the data caches

• interrupts and exceptions

• memory management units (MMUs)

• pipelined processors: the classical five-stage pipeline is extended by two pipeline

stages for address translation

• local interrupt controller (ICs) supporting inter-processor interrupts (IPIs)

• I/O-interrupt controller and a disk

Product Details

ISBN-13:	9783030432423
Publisher:	Springer International Publishing
Publication date:	05/10/2020
Series:	Lecture Notes in Computer Science , #9999
Edition description:	1st ed. 2020
Pages:	628
Product dimensions:	6.10(w) x 9.25(h) x (d)

Table of Contents

Introductory material.- on hierarchical hardware design.- hardware library.- basic processor design.- pipelining.- cache memory systems.- interrupt mechanism.- self modification, instruction buffer and nondeterministic ISA.- memory management units.- store buffers.- multi-core processors.- advanced programmable interrupt controllers (APICs).- adding a disk.- I/O apic.