Advanced Computer Arithmetic Design / Edition 1

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Overview

Innovative techniques and cutting-edge research in computer arithmetic design
Computer arithmetic is a fundamental discipline that drives many modern digital technologies. High-performance VLSI implementations of 3-D graphics, encryption, streaming digital audio and video, and signal processing all require fast and efficient computer arithmetic algorithms. The demand for these fast implementations has led to a wealth of new research in innovative techniques and designs.
Advanced Computer Arithmetic Design is the result of ten years of effort at Stanford University under the Sub-Nanosecond Arithmetic Processor (SNAP) project, which author Michael Flynn directs. Written with computer designers and researchers in mind, this volume focuses on design, rather than on other aspects of computer arithmetic such as number systems, representation, or precision.
Each chapter begins with a review of conventional design approaches, analyzes the possibilities for improvement, and presents new research that advances the state of the art. The authors present new data in these vital areas:
* Addition and the Ling adder
* Improvements to floating-point addition
* Encoding to reduce execution times for multiplication
* The effects of technology scaling on multiplication
* Techniques for floating-point division
* Approximation techniques for high-level functions such as square root, logarithms, and trigonometric functions
* Assessing cost performance of arithmetic units
* Clocking to increase computer operation frequency
* New implementation of continued fractions to the approximation of functions
This volume presents the results of a decade's research in innovative and progressive design techniques. Covering all the most important research topics in the field, Advanced Computer Arithmetic Design is the most up-to-date and comprehensive treatment of new research currently available.

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Editorial Reviews

From the Publisher
"Drawing from a decade of research at Stanford University's Sub-Nanosecond Arithmetic Processor...[the authors]...explain arithmetic design to computer designers and researchers." (SciTech Book News Vol. 25, No. 2 June 2001)
SciTech Book
Drawing from a decade of research at Stanford University's Sub-Nanosecond Arithmetic Processor...[the authors]...explain arithmetic design to computer designers and researchers.
SciTech Book
Drawing from a decade of research at Stanford University's Sub-Nanosecond Arithmetic Processor...[the authors]...explain arithmetic design to computer designers and researchers.
Booknews
Drawing from a decade of research at Stanford University's Sub- Nanosecond Arithmetic Processor, which Flynn directs, he and Oberman, formerly also at Stanford, explain arithmetic design to computer designers and researchers. They do not pay much attention to other aspects of arithmetic, such as number systems, representation, or precision. Each chapter reviews conventional design approaches, analyzes the possibilities for improvement, and presents relevant research findings. Among the topics are addition and the Ling adder, improvements to floating-point addition, and the effects of technological scaling on multiplication. Annotation c. Book News, Inc., Portland, OR (booknews.com)
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Product Details

  • ISBN-13: 9780471412090
  • Publisher: Wiley
  • Publication date: 4/28/2001
  • Edition description: New Edition
  • Edition number: 1
  • Pages: 344
  • Product dimensions: 6.38 (w) x 9.49 (h) x 0.81 (d)

Meet the Author

MICHAEL J. FLYNN is Director of the Sub-Nanosecond Arithmetic Processor (SNAP) project at Stanford University. For the past decade, he has been the leading source of published research in the area of computer arithmetic design. Stuart F. Oberman earned his Phd at Stanford University and is currently manager of VLSI Design at Nishan Systems, San Jose, California. He previously worked at AMD, where he was the architect of the Athlon floating-point unit. His research interests include new algorithms for high-speed computer arithmetic, high-speed switch-fabric design, and architectures for high-throughput network processors.

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Table of Contents

Preface.

Acknowledgments.

Notation.

Integer Addition.

Floating-Point Addition.

Multiplication with Partially Redundant Multiples.

Multiplier Topologies.

Technology Scaling Effects on Multipliers.

Design Issues in Division.

Minimizing the Complexity of SRT Tables.

Very High-Radix Division.

Using a Multiplier for Function Approximation.

FUPA.

High-Speed Clocking Using Wave Pipelining.

Rational Arithmetic.

Bibliography.

Index.

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