Advanced Formal Verification / Edition 1

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Overview

Modern circuits may contain up to several hundred million transistors. In the meantime it has been observed that verification becomes the major bottleneck in design flows, i.e. up to 80% of the overall design costs are due to verification. This is one of the reasons why recently several methods have been proposed as alternatives to classical simulation. Simulation alone cannot guarantee sufficient coverage of the design resulting in bugs that may remain undetected. As alternatives formal verification techniques have been proposed. Instead of simulating a design the correctness is proven by formal techniques. There are many different areas where these approaches can be used, like equivalence checking, property checking or symbolic simulation. Meanwhile these methods have been successfully applied in many industrial projects and have become the state-of-the-art technique in several fields. But the deployment of the existing tools in real-world projects also showed the weaknesses and problems of formal verification techniques. This gave motivating impulses for tool developers and researchers. Advanced Formal Verification shows latest developments in the verification domain from the perspectives of the user and the developer. World leading experts describe the underlying methods of today's verification tools and describe various scenarios from industrial practice. In the first part of the book the core techniques of today's formal verification tools, like SAT and BDDs are addressed. In addition, instances known to be difficult, like multipliers, are studied. The second part gives insight in professional tools and the underlying methodology, like property checking and assertion based verification. Finally, to cope with complete system on chip designs also analog components have to be considered. In this book the state-of-the-art in many important fields of formal verification is described. Besides the description of the most recent

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Product Details

  • ISBN-13: 9781402077210
  • Publisher: Springer US
  • Publication date: 1/31/2004
  • Series: Falk Symposium Series
  • Edition description: 2004
  • Edition number: 1
  • Pages: 628
  • Product dimensions: 0.75 (w) x 6.14 (h) x 9.21 (d)

Table of Contents

Preface
Contributing Authors
Introduction
1 What Sat-Solvers can and cannot do 1
2 Advancements in mixed BDD and SAT techniques 45
3 Equivalence Checking of Arithmetic Circuits 77
4 Application of Property Checking and Underlying Techniques 125
5 Assertion-Based Verification 167
6 Formal Verification for Nonlinear Analog Systems 205
Index 247
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