Advanced Multi-Microprocessor Bus Architectures

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Provides an historical perspective on the development of standard open bus architectures, with papers by scientists and engineers who developed the field. Topics include bus physics and protocols, system architectures, board and interface design, cache coherence, real-time systems, and performance evaluation and testing. Includes a list of bus acronyms and a glossary. For hardware and systems engineers, managers, and educators. Annotation c. Book News, Inc., Portland, OR (booknews.com)
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Product Details

  • ISBN-13: 9780818663277
  • Publisher: IEEE Computer Society Press
  • Publication date: 1/1/1995
  • Pages: 472
  • Product dimensions: 8.50 (w) x 11.00 (h) x 1.00 (d)

Table of Contents

Preface
Acknowledgments
Introduction: Fundamental Problems of Bus Design 1
Computer Buses - A Tutorial 10
MicroStandards Special Feature: A Comparison of 32-Bit Buses 26
The Proposed IEEE 896 Futurebus - A Solution to the Bus Driving Problem 37
The Physics of Driving Backplane Buses 42
Wire-OR Logic on Transmission Lines 46
Metastable States in Asynchronous Digital Systems: Avoidable or Unavoidable? 51
Improved Control Acquisition Scheme for the IEEE 896 Futurebus 73
The Distributed Arbitration Protocol 85
An Advanced Communication Protocol for the Proposed IEEE 896 Futurebus 90
P1296: The Interprocessor Communication Standard 105
The Proposed SSBLT Standard Doubles the VME64 Transfer Rate 111
Design of a Family of Multi-Microprocessor Systems 121
Introduction to the Fastbus 131
Overview of Multibus II Architecture 140
The VME Subsystem Bus 150
Multiplexed Buses: The Endian Wars Continue 159
Futurebus+ as an I/O Bus: Profile B 172
A Bus on a Diet - The Serial Bus Alternative: An Introduction to the P1394 High Performance Serial Bus 180
The Scalable Coherent Interface and Related Standards Projects 195
Designing a High-Performance VME-to-FDDI Controller Board 211
Multibus II-VME Interface 223
Interfacing I/O to the Multibus II PSB 233
A Gate Array Implementation of a Fault-Tolerant Bus Interface Unit Based on NuBus Protocols 237
A Futurebus Interface from Off-the-Shelf Parts 244
A Class of Compatible Cache Consistency Protocols and Their Support by the IEEE Futurebus 261
Multiprocessing on the Nubus Using Cache Inhibited Pages 271
Distributed-Directory Scheme: Scalable Coherent Interface 277
Verification of the Futurebus+ Cache Coherence Protocol 281
Specification and Verification of a Distributed Real-Time Arbitration Protocol 301
Real-Time Computing with IEEE Futurebus+ 311
What Every Engineer Needs to Know about Rate-Monotonic Scheduling: A Tutorial 321
Software Design for Real-Time Multiprocessor VMEbus Systems 336
Evaluating Design Choices for Shared Bus Multiprocessors in a Throughput-Oriented Environment 349
A Generalized Stochastic Petri Net Model of Multibus II 370
Evaluation of Futurebus+ for a GMMP Multiprocessor 376
Performance of the SCI Ring 380
Conformance Testing of VMEbus and Multibus II Products 392
Why Open, and Why Buses? 404
The Many Dimensions of Scalability 411
List of Bus Acronyms 415
Glossary of Bus Terms 416
Bibliography 423
Subject Index 455
About the Author 459
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