Analysis and Design of Resilient VLSI Circuits: Mitigating Soft Errors and Process Variations

by Rajesh Garg

Overview

This monograph is motivated by the challenges faced in designing reliable VLSI systems in modern VLSI processes. The reliable operation of integrated circuits (ICs) has become increasingly difficult to achieve in the deep submicron (DSM) era. With continuouslydecreasing device feature sizes, combinedwith lower supply voltages and higher operating frequencies, the noise immunity of VLSI circuits is decreasing alarmingly. Thus, VLSI circuits are becoming more vulnerable to noise effects such as crosstalk, power supply variations, and radiation-inducedsoft errors. Among these noise sources, soft errors(or error caused by radiation particle strikes) have become an increasingly troublesome issue for memory arrays as well as c- binational logic circuits. Also, in the DSM era, process variations are increasing at a significant rate, making it more difficult to design reliable VLSI circuits. Hence, it is important to efficiently design robust VLSI circuits that are resilient to radiation particle strikes and process variations. The work presented in this research mo- graph presents several analysis and design techniques with the goal of realizing VLSI circuits, which are radiation and process variation tolerant.

Product Details

ISBN-13:	9781441909305
Publisher:	Springer US
Publication date:	11/16/2009
Edition description:	2010
Pages:	212
Product dimensions:	6.40(w) x 9.30(h) x 0.80(d)

Table of Contents

Soft Errors.- Analytical Determination of Radiation-induced Pulse Width in Combinational Circuits.- Analytical Determination of the Radiation-induced Pulse Shape.- Modeling Dynamic Stability of SRAMs in the Presence of Radiation Particle Strikes.- 3D Simulation and Analysis of the Radiation Tolerance of Voltage Scaled Digital Circuits.- Clamping Diode-based Radiation Tolerant Circuit Design Approach.- Split-output-based Radiation Tolerant Circuit Design Approach.- Process Variations.- Sensitizable Statistical Timing Analysis.- A Variation Tolerant Combinational Circuit Design Approach Using Parallel Gates.- Process Variation Tolerant Single-supply True Voltage Level Shifter.- Conclusions and Future Directions.