Behavioral Synthesis : Digital System Design Using the Synopsys Behavioral Compiler / Edition 1

Hardcover (Print)
Used and New from Other Sellers
Used and New from Other Sellers
from $2.98
Usually ships in 1-2 business days
(Save 96%)
Other sellers (Hardcover)
  • All (13) from $2.98   
  • New (4) from $46.80   
  • Used (9) from $2.98   
Close
Sort by
Page 1 of 1
Showing All
Note: Marketplace items are not eligible for any BN.com coupons and promotions
$46.80
Seller since 2005

Feedback rating:

(49821)

Condition:

New — never opened or used in original packaging.

Like New — packaging may have been opened. A "Like New" item is suitable to give as a gift.

Very Good — may have minor signs of wear on packaging but item works perfectly and has no damage.

Good — item is in good condition but packaging may have signs of shelf wear/aging or torn packaging. All specific defects should be noted in the Comments section associated with each item.

Acceptable — item is in working order but may show signs of wear such as scratches or torn packaging. All specific defects should be noted in the Comments section associated with each item.

Used — An item that has been opened and may show signs of wear. All specific defects should be noted in the Comments section associated with each item.

Refurbished — A used item that has been renewed or updated and verified to be in proper working condition. Not necessarily completed by the original manufacturer.

New
Shrink-wrapped NEW book

Ships from: Columbia, MO

Usually ships in 1-2 business days

  • Standard, 48 States
  • Standard (AK, HI)
  • Express, 48 States
  • Express (AK, HI)
$59.47
Seller since 2015

Feedback rating:

(365)

Condition: New
Brand New Item.

Ships from: Chatham, NJ

Usually ships in 1-2 business days

  • Canadian
  • International
  • Standard, 48 States
  • Standard (AK, HI)
  • Express, 48 States
  • Express (AK, HI)
$60.00
Seller since 2015

Feedback rating:

(241)

Condition: New
Brand new.

Ships from: acton, MA

Usually ships in 1-2 business days

  • Standard, 48 States
  • Standard (AK, HI)
$62.27
Seller since 2008

Feedback rating:

(215)

Condition: New

Ships from: Chicago, IL

Usually ships in 1-2 business days

  • Standard, 48 States
  • Standard (AK, HI)
Page 1 of 1
Showing All
Close
Sort by

Overview

Behavioral synthesis is now a reality. After nearly twenty years of academic and industrial research and development, designers are reaping the rewards of this technology, which brings increased productivity, improved design quality, and faster time to market.

This book gives a designer's-eye view of this exciting new EDA technology. The first six chapters provide a detailed description of what goes on under the hood of an industrial-strength behavioral synthesis product, the Synopsys Behavioral Compiler, with copious notes and tips on how to use this knowledge to get the most out of this powerful new tool.

  • Introduction to the behavioral design flow
  • Behavioral synthesis representations and processes
  • Writing HDL descriptions for behavioral synthesis
  • Managing I/O timing
  • Behavioral Compiler commands and options
  • Interpreting error messages

The next five chapters provide detailed case studies, representing a variety of design problems:

  • IIR and FIR filters
  • Video compression and translation from C to HDLs
  • Data encryption
  • Packet routing

The examples are given in both VHDL and Verilog. Machine-readable versions, along with complete synthesis reports, are provided on the accompanying diskette (requires Syopsys Behavioral Compiler to synthesize).

Read More Show Less

Editorial Reviews

Booknews
A book/disk package describing a behavioral synthesis product, detailing behavioral design flow and behavioral synthesis processes, and showing how to write HDL descriptions, manage I/O timing, and interpret error messages. Offers case studies representing design problems concerning IIR and FIR filters, video compression and translation from C to HDL, and data encryption. The accompanying disk requires the Synopsis Behavioral Compiler to synthesize. For working engineers, engineering managers, and advanced students. Annotation c. Book News, Inc., Portland, OR (booknews.com)
Read More Show Less

Product Details

  • ISBN-13: 9780135692523
  • Publisher: Prentice Hall Professional Technical Reference
  • Publication date: 5/24/1996
  • Edition number: 1
  • Pages: 231
  • Product dimensions: 7.27 (w) x 9.55 (h) x 1.09 (d)

Read an Excerpt

PREFACE: Over the past three decades we have seen an astonishing increase in the scale of circuits we routinely design. This increase came about because of advances in lithography and silicon processing. The increase in the number of available transistors has resulted in numerous changes in design techniques and methodologies, as engineers have struggled to master the complexities of ever-increasing numbers of elements within a roughly constant development time.

During this period we have also witnessed the appearance of increasingly powerful synthesis and verification tools. These tools have helped us to master the possibilities inherent in our ability to manufacture ever-greater numbers of transistors. This is not always a comfortable process: engineers must choose between new, comparatively untried tools, which at least hold out the promise of handling the current level of complexity, and older, better-understood tools whose per-transistor effort level remains roughly constant.

This book describes methodologies for using a comparatively new class of synthesis tools, called variously "behavioral synthesis", "high-level synthesis" (HLS), and other less common names. These tools can radically reduce the level of effort needed to design a circuit of a given complexity; or conversely, they allow a much more complex design to be constructed with about the same effort. Behavioral synthesis does this be relieving the engineer of the burden of defining state machines and assigning operations to states. This allows the user to consider a variety of design alternatives, over a wide cost/performance range, with almost no effort beyond the construction of the initialfunctional description.

The increased abstraction of a high-level specification also radically decreases the size of the initial functional description, when compared to descriptions written at the next lower level of abstraction; usually by a factor of three to five, and sometimes much more. The result of this decrease in description size is a corresponding decrease in the number of bugs a user will tend to create; in the number of decisions that must be made; in the time it takes to construct the description; and in the amount of effort needed to understand it afterward.

The methodologies described here are based on hardware-description languages (HDLs). In order to get the most out of the tools, you need a "good style" of writing HDL descriptions. Good style requires an understanding of what's going on inside the behavioral synthesis system; it also requires that you understand how you will verify your design both before and after synthesis has been performed. These issues are closely interrelated. A useful analogy is to a discussion of goo C language style, which would range all the way from how memory is treated to the design of algorithms for implementation on a machine with a single memory and a single instruction stream. Clearly, some styles of expression are better than others; but to understand why, we need at least some understanding of how our C program is going to be compiled, executed, tested, and debugged. The case is similar with HDL descriptions for HLS: we cannot expect to write good code by accident.

This book is intended for the working engineer, the engineering manager, and the student. The engineer will find in these pages ways to describe and synthesize designs using behavioral synthesis; in addition, he or she will find ways to characterize and debug design descriptions, and ways to get the most out of a behavioral synthesis tool. The engineering manager will obtain an introduction to a new way of thinking about digital design, a sense of the kinds of problems for which it is useful, and a premonitory glimpse of the kinds of difficulties that will have to be resolved. The student will be exposed to description of a working, commercially viable tool, with emphasis on the nuts and bolts from an industrial and user perspective. All readers will get an introduction to a leading behavioral synthesis tool, the Synopsys Behavioral Compiler, which is used as a basis for discussion, and of which I was one of the builders. This book is loosely based on Version 3.4 of the tool; but in places I will refer to features that are expected to be present in future releases as well.

This is not an academic or theoretical treatment of behavioral synthesis. There are a number of very good general theoretical books and articles on the subject; (4). (5), (13), and (14) are good examples. This book is intended to provide a working understanding of an industrial approach to behavioral synthesis. Thus it is a supplement to a theoretical treatment rather than a substitute for one. By the same token, however, this book describes many real problems and details of behavioral synthesis that have received little attention in more theoretically oriented circles.

The first six chapters of this book contain a general description of behavioral synthesis and of Behavioral Compiler in particular.
Chapter 1 is an introduction to the general design flow and the behavioral synthesis flow. This introduction will orient the reader and provide motivation and background material for the subsequent chapters.
Chapter 2 discusses the inputs, structure and internal representations, and out-puts of a behavioral synthesis system: the Synopsys Behavioral Compiler. This will help you to understand what is happening inside the synthesis process, and to understand the things that BC tells you.
Chapter 3 gives a discussion of basic HDL description styles and constructs that accomplish specific design goals; for example, how to create a specific state diagram, how to cause a memory to be instantiated, how to handle I/O protocals, and so on. The emphasis here is on the ways in which HDL semantics imply various kinds of hardware structures.
Chapter 4 discusses I/O timing in the HDL description and different models of equivalence between the pre- and post-synthesis designs. These interactions have important competences for the ways in which HDL descriptions can be written and synthesized.
Chapter 5 describes ways in which you can drive Behavioral Compiler by using commands and directives. This complements the discussion of Chapters 3 and 4, which show how to achieve specific goals using HDL semantics only.
Chapter 6 gives a description of the kind of output the user of behavioral synthesis can expect to see. This chapter necessarily relies most heavily on the current Synopsys product, but the general strategy and descriptions of basic reporting styles should prove useful beyond that context as well.

The latter part of this book is divided into case studies; each has been chosen for its ability to illustrate some important feature of behavioral synthesis or of the overall process. The case studies presented here are also included on the diskette that accompanies this book; you can study them, simulate them, synthesize them, and change them as you will. The examples used are the following.
Chapter 7 describes an FIR filter, which illustrates a basic behavioral description style for cycle-fixed I/O mode and the construction of handshaking I/O protocol. More advanced performance- tuning techniques are also used, including the use pipelined components.
Chapter 8 describes an IIR filter, which illustrates basic behavioral specification style for cycle-fixed I/O mode and the construction of handshaking I/O protocol. More advanced performance- tuning techniques are also use, including the use of pipelined components.
Chapter 9 describes an inverse discrete cosine transform This chapter begins with a small program fragment (a pair of matrix multiplications) written in C, and then gradually transforms it from a naive translation that doesn't work very well into a much more sophisticated version. This example also provides you with experience in using memories.
Chapter 10 describes the Data Encryption Standard, which illustrates the synthesis of a design consisting almost entirely of random logic. This example also shows the use of DesignWare to encapsulate random logic for sharing.
Chapter 11 describes a packet router, which is an example of control-dominated design with memory.

There are also two appendices. Appendix A gives a brief description of the use of DesignWare in conjunction with the other Synopsys tools; and Appendix B gives an overview of the synthesizable subsets of VHDL and Verilog that are supported by the current Synopsys products.

Typographical conventions.
It is usually pretty obvious when a word or other symbol is coming from a different language or namespace than that of the base text. For example, if I use the term "entity" in the context of a VHDL hardware description, most readers will not be fooled: they won't go looking for the definition of "entity" in a dictionary. Instead, they will semi-automatically refer to the namespace of VHDL constructs. This is just common sense and shared background.
I have therefore relied on the following guideline: where the namespace of a symbol is ambiguous, and there is a sense under which the ambiguity might be resolved incorrectly, I will use a different font to indicate that the symbol is taken from another namespace than that of written English. For example, I might discuss the architecture of a CPU; here there is an ambiguity, because I might mean either the VHDL architecture, which is taken from VHDL construct. Sometimes it might not matter: a VHDL loop is in most cases just another loop, and deserves no special treatment. In such a case I will use the convention that makes the text flow most smoothly.
The other case where I will use typography to set off a symbol taken from a non-English namespace is where a sentence might become awkward or grammatically incorrect if the symbol is not set off in some way. For example, in this sentence the mathematical variable a would look very strange if it were not set in italics, and the VHDL variable index would be misleading without the special font.
But excessive use of typographical variations blights many an otherwise readable text. Setting off every keyword of such a populous language as VHDL would quickly result in the textual analog of an "angry fruit salad" graphical user interface. So where neither grammar not ambiguity constrains the choices of language and typography, I will stick to standard English set in plain Roman.
Read More Show Less

Table of Contents

Preface
1 Introduction 1
2 Behavioral Compiler 14
3 HDL Descriptions 32
4 I/O modes 57
5 Explicit Directives and Constraints 74
6 Reports 83
7 FIR filter 99
8 HR filter: handshaking I/O protocol 125
9 The Inverse Discrete Cosine Transform: C to HDL 158
10 The Data Encryption Standard: Random Logic 184
11 Packet router 195
A Constructing Design Ware 202
B Synthesizable Subsets 221
Read More Show Less

Preface

Over the past three decades we have seen an astonishing increase in the scale of circuits we routinely design. This increase came about because of advances in lithography and silicon processing. The increase in the number of available transistors has resulted in numerous changes in design techniques and methodologies, as engineers have struggled to master the complexities of ever-increasing numbers of elements within a roughly constant development time.

During this period we have also witnessed the appearance of increasingly powerful synthesis and verification tools. These tools have helped us to master the possibilities inherent in our ability to manufacture ever-greater numbers of transistors. This is not always a comfortable process: engineers must choose between new, comparatively untried tools, which at least hold out the promise of handling the current level of complexity, and older, better-understood tools whose per-transistor effort level remains roughly constant.

This book describes methodologies for using a comparatively new class of synthesis tools, called variously "behavioral synthesis", "high-level synthesis" (HLS), and other less common names. These tools can radically reduce the level of effort needed to design a circuit of a given complexity; or conversely, they allow a much more complex design to be constructed with about the same effort. Behavioral synthesis does this be relieving the engineer of the burden of defining state machines and assigning operations to states. This allows the user to consider a variety of design alternatives, over a wide cost/performance range, with almost no effort beyond the construction of the initial functional description.

The increased abstraction of a high-level specification also radically decreases the size of the initial functional description, when compared to descriptions written at the next lower level of abstraction; usually by a factor of three to five, and sometimes much more. The result of this decrease in description size is a corresponding decrease in the number of bugs a user will tend to create; in the number of decisions that must be made; in the time it takes to construct the description; and in the amount of effort needed to understand it afterward.

The methodologies described here are based on hardware-description languages (HDLs). In order to get the most out of the tools, you need a "good style" of writing HDL descriptions. Good style requires an understanding of what's going on inside the behavioral synthesis system; it also requires that you understand how you will verify your design both before and after synthesis has been performed. These issues are closely interrelated. A useful analogy is to a discussion of goo C language style, which would range all the way from how memory is treated to the design of algorithms for implementation on a machine with a single memory and a single instruction stream. Clearly, some styles of expression are better than others; but to understand why, we need at least some understanding of how our C program is going to be compiled, executed, tested, and debugged. The case is similar with HDL descriptions for HLS: we cannot expect to write good code by accident.

This book is intended for the working engineer, the engineering manager, and the student. The engineer will find in these pages ways to describe and synthesize designs using behavioral synthesis; in addition, he or she will find ways to characterize and debug design descriptions, and ways to get the most out of a behavioral synthesis tool. The engineering manager will obtain an introduction to a new way of thinking about digital design, a sense of the kinds of problems for which it is useful, and a premonitory glimpse of the kinds of difficulties that will have to be resolved. The student will be exposed to description of a working, commercially viable tool, with emphasis on the nuts and bolts from an industrial and user perspective. All readers will get an introduction to a leading behavioral synthesis tool, the Synopsys Behavioral Compiler, which is used as a basis for discussion, and of which I was one of the builders. This book is loosely based on Version 3.4 of the tool; but in places I will refer to features that are expected to be present in future releases as well.

This is not an academic or theoretical treatment of behavioral synthesis. There are a number of very good general theoretical books and articles on the subject; (4). (5), (13), and (14) are good examples. This book is intended to provide a working understanding of an industrial approach to behavioral synthesis. Thus it is a supplement to a theoretical treatment rather than a substitute for one. By the same token, however, this book describes many real problems and details of behavioral synthesis that have received little attention in more theoretically oriented circles.

The first six chapters of this book contain a general description of behavioral synthesis and of Behavioral Compiler in particular.
Chapter 1 is an introduction to the general design flow and the behavioral synthesis flow. This introduction will orient the reader and provide motivation and background material for the subsequent chapters.
Chapter 2 discusses the inputs, structure and internal representations, and out-puts of a behavioral synthesis system: the Synopsys Behavioral Compiler. This will help you to understand what is happening inside the synthesis process, and to understand the things that BC tells you.
Chapter 3 gives a discussion of basic HDL description styles and constructs that accomplish specific design goals; for example, how to create a specific state diagram, how to cause a memory to be instantiated, how to handle I/O protocals, and so on. The emphasis here is on the ways in which HDL semantics imply various kinds of hardware structures.
Chapter 4 discusses I/O timing in the HDL description and different models of equivalence between the pre- and post-synthesis designs. These interactions have important competences for the ways in which HDL descriptions can be written and synthesized.
Chapter 5 describes ways in which you can drive Behavioral Compiler by using commands and directives. This complements the discussion of Chapters 3 and 4, which show how to achieve specific goals using HDL semantics only.
Chapter 6 gives a description of the kind of output the user of behavioral synthesis can expect to see. This chapter necessarily relies most heavily on the current Synopsys product, but the general strategy and descriptions of basic reporting styles should prove useful beyond that context as well.

The latter part of this book is divided into case studies; each has been chosen for its ability to illustrate some important feature of behavioral synthesis or of the overall process. The case studies presented here are also included on the diskette that accompanies this book; you can study them, simulate them, synthesize them, and change them as you will. The examples used are the following.
Chapter 7 describes an FIR filter, which illustrates a basic behavioral description style for cycle-fixed I/O mode and the construction of handshaking I/O protocol. More advanced performance- tuning techniques are also used, including the use pipelined components.
Chapter 8 describes an IIR filter, which illustrates basic behavioral specification style for cycle-fixed I/O mode and the construction of handshaking I/O protocol. More advanced performance- tuning techniques are also use, including the use of pipelined components.
Chapter 9 describes an inverse discrete cosine transform This chapter begins with a small program fragment (a pair of matrix multiplications) written in C, and then gradually transforms it from a naive translation that doesn't work very well into a much more sophisticated version. This example also provides you with experience in using memories.
Chapter 10 describes the Data Encryption Standard, which illustrates the synthesis of a design consisting almost entirely of random logic. This example also shows the use of DesignWare to encapsulate random logic for sharing.
Chapter 11 describes a packet router, which is an example of control-dominated design with memory.

There are also two appendices. Appendix A gives a brief description of the use of DesignWare in conjunction with the other Synopsys tools; and Appendix B gives an overview of the synthesizable subsets of VHDL and Verilog that are supported by the current Synopsys products.

Typographical conventions.
It is usually pretty obvious when a word or other symbol is coming from a different language or namespace than that of the base text. For example, if I use the term "entity" in the context of a VHDL hardware description, most readers will not be fooled: they won't go looking for the definition of "entity" in a dictionary. Instead, they will semi-automatically refer to the namespace of VHDL constructs. This is just common sense and shared background.
I have therefore relied on the following guideline: where the namespace of a symbol is ambiguous, and there is a sense under which the ambiguity might be resolved incorrectly, I will use a different font to indicate that the symbol is taken from another namespace than that of written English. For example, I might discuss the architecture of a CPU; here there is an ambiguity, because I might mean either the VHDL architecture, which is taken from VHDL construct. Sometimes it might not matter: a VHDL loop is in most cases just another loop, and deserves no special treatment. In such a case I will use the convention that makes the text flow most smoothly.
The other case where I will use typography to set off a symbol taken from a non-English namespace is where a sentence might become awkward or grammatically incorrect if the symbol is not set off in some way. For example, in this sentence the mathematical variable a would look very strange if it were not set in italics, and the VHDL variable index would be misleading without the special font.
But excessive use of typographical variations blights many an otherwise readable text. Setting off every keyword of such a populous language as VHDL would quickly result in the textual analog of an "angry fruit salad" graphical user interface. So where neither grammar not ambiguity constrains the choices of language and typography, I will stick to standard English set in plain Roman.
Read More Show Less

Customer Reviews

Be the first to write a review
( 0 )
Rating Distribution

5 Star

(0)

4 Star

(0)

3 Star

(0)

2 Star

(0)

1 Star

(0)

Your Rating:

Your Name: Create a Pen Name or

Barnes & Noble.com Review Rules

Our reader reviews allow you to share your comments on titles you liked, or didn't, with others. By submitting an online review, you are representing to Barnes & Noble.com that all information contained in your review is original and accurate in all respects, and that the submission of such content by you and the posting of such content by Barnes & Noble.com does not and will not violate the rights of any third party. Please follow the rules below to help ensure that your review can be posted.

Reviews by Our Customers Under the Age of 13

We highly value and respect everyone's opinion concerning the titles we offer. However, we cannot allow persons under the age of 13 to have accounts at BN.com or to post customer reviews. Please see our Terms of Use for more details.

What to exclude from your review:

Please do not write about reviews, commentary, or information posted on the product page. If you see any errors in the information on the product page, please send us an email.

Reviews should not contain any of the following:

  • - HTML tags, profanity, obscenities, vulgarities, or comments that defame anyone
  • - Time-sensitive information such as tour dates, signings, lectures, etc.
  • - Single-word reviews. Other people will read your review to discover why you liked or didn't like the title. Be descriptive.
  • - Comments focusing on the author or that may ruin the ending for others
  • - Phone numbers, addresses, URLs
  • - Pricing and availability information or alternative ordering information
  • - Advertisements or commercial solicitation

Reminder:

  • - By submitting a review, you grant to Barnes & Noble.com and its sublicensees the royalty-free, perpetual, irrevocable right and license to use the review in accordance with the Barnes & Noble.com Terms of Use.
  • - Barnes & Noble.com reserves the right not to post any review -- particularly those that do not follow the terms and conditions of these Rules. Barnes & Noble.com also reserves the right to remove any review at any time without notice.
  • - See Terms of Use for other conditions and disclaimers.
Search for Products You'd Like to Recommend

Recommend other products that relate to your review. Just search for them below and share!

Create a Pen Name

Your Pen Name is your unique identity on BN.com. It will appear on the reviews you write and other website activities. Your Pen Name cannot be edited, changed or deleted once submitted.

 
Your Pen Name can be any combination of alphanumeric characters (plus - and _), and must be at least two characters long.

Continue Anonymously

    If you find inappropriate content, please report it to Barnes & Noble
    Why is this product inappropriate?
    Comments (optional)