High-Speed Digital System Design: A Handbook of Interconnect Theory and Design Practices / Edition 1

High-Speed Digital System Design: A Handbook of Interconnect Theory and Design Practices / Edition 1

by Stephen H. Hall
     
 

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ISBN-10: 0471360902

ISBN-13: 2900471360901

Pub. Date: 09/28/2000

Publisher: Wiley

An understanding of high-speed interconnect phenomena is essential for digital designers who must deal with the challenges posed by the ever-increasing operating speeds of today's microprocessors. This book provides a much-needed, practical guide to the state of the art of modern digital system design, combining easily accessible explanations with immensely useful

Overview

An understanding of high-speed interconnect phenomena is essential for digital designers who must deal with the challenges posed by the ever-increasing operating speeds of today's microprocessors. This book provides a much-needed, practical guide to the state of the art of modern digital system design, combining easily accessible explanations with immensely useful problem-solving strategies. Written by three leading Intel engineers, High-Speed Digital System Design clarifies difficult and often neglected topics involving the effects of high frequencies on digital buses and presents a variety of proven techniques and application examples. Extensive appendices, formulas, modeling techniques as well as hundreds of figures are also provided.

Product Details

ISBN-13:
2900471360901
Publisher:
Wiley
Publication date:
09/28/2000
Edition description:
New Edition
Pages:
362

Table of Contents

Prefacexi
1.The Importance of Interconnect Design1
1.1The Basics2
1.2The Past and the Future4
2.Ideal Transmission Line Fundamentals7
2.1Transmission Line Structures on a PCB or MCM7
2.2Wave Propagation8
2.3Transmission Line Parameters9
2.3.1Characteristic Impedance11
2.3.2Propagation Velocity, Time, and Distance14
2.3.3Equivalent Circuit Models for SPICE Simulation15
2.4Launching Initial Wave and Transmission Line Reflections18
2.4.1Initial Wave18
2.4.2Multiple Reflections19
2.4.3Effect of Rise Time on Reflections26
2.4.4Reflections From Reactive Loads28
2.4.5Termination Schemes to Eliminate Reflections32
2.5Additional Examples36
2.5.1Problem36
2.5.2Goals36
2.5.3Calculating the Cross-Sectional Geometry of the PCB37
2.5.4Calculating the Propagation Delay38
2.5.5Determining the Wave Shape Seen at the Receiver39
2.5.6Creating an Equivalent Circuit40
3.Crosstalk42
3.1Mutual Inductance and Mutual Capacitance42
3.2Inductance and Capacitance Matrix43
3.3Field Simulators45
3.4Crosstalk-Induced Noise45
3.5Simulating Crosstalk Using Equivalent Circuit Models51
3.6Crosstalk-Induced Flight Time and Signal Integrity Variations52
3.6.1Effect of Switching Patterns on Transmission Line Performance53
3.6.2Simulating Traces in a Multiconductor System Using a Single-Line Equivalent Model59
3.7Crosstalk Trends62
3.8Termination of Odd- and Even-Mode Transmission Line Pairs65
3.8.1Pi Termination Network65
3.8.2T Termination Network66
3.9Minimization of Crosstalk67
3.10Additional Examples68
3.10.1Problem69
3.10.2Goals70
3.10.3Determining the Maximum Crosstalk-Induced Impedance and Velocity Swing70
3.10.4Determining if Crosstalk Will Induce False Triggers72
4.Nonideal Interconnect Issues74
4.1Transmission Line Losses74
4.1.1Conductor DC Losses75
4.1.2Dielectric DC Losses75
4.1.3Skin Effect76
4.1.4Frequency-Dependent Dielectric Losses87
4.2Variations in the Dielectric Constant91
4.3Serpentine Traces92
4.4Intersymbol Interference95
4.5Effects of 90[deg] Bends97
4.6Effect of Topology99
5.Connectors, Packages, and Vias102
5.1Vias102
5.2Connectors104
5.2.1Series Inductance104
5.2.2Shunt Capacitance105
5.2.3Connector Crosstalk105
5.2.4Effects of Inductively Coupled Connector Pin Fields106
5.2.5EMI109
5.2.6Connector Design Guidelines110
5.3Chip Packages112
5.3.1Common Types of Packages113
5.3.2Creating a Package Model117
5.3.3Effects of a Package121
5.3.4Optimal Pin-Outs127
6.Nonideal Return Paths, Simultaneous Switching Noise, and Power Delivery129
6.1Nonideal Current Return Paths129
6.1.1Path of Least Inductance129
6.1.2Signals Traversing a Ground Gap130
6.1.3Signals That Change Reference Planes134
6.1.4Signals Referenced to a Power or a Ground Plane135
6.1.5Other Nonideal Return Path Scenarios140
6.1.6Differential Signals140
6.2Local Power Delivery Networks141
6.2.1Determining the Local Decoupling Requirements for High-Speed I/O144
6.2.2System-Level Power Delivery147
6.2.3Choosing a Decoupling Capacitor149
6.2.4Frequency Response of a Power Delivery System150
6.3SSO/SSN151
6.3.1Minimizing SSN154
7.Buffer Modeling156
7.1Types of Models157
7.2Basic CMOS Output Buffer157
7.2.1Basic Operation157
7.2.2Linear Modeling of the CMOS Buffer164
7.2.3Behavioral Modeling of the Basic CMOS Buffer172
7.3Output Buffers That Operate in the Saturation Region175
7.4Conclusions177
8.Digital Timing Analysis178
8.1Common-Clock Timing178
8.1.1Common-Clock Timing Equations180
8.2Source Synchronous Timing183
8.2.1Source Synchronous Timing Equations186
8.2.2Deriving Source Synchronous Timing Equations from an Eye Diagram189
8.2.3Alternative Source Synchronous Schemes191
8.3Alternative Bus Signaling Techniques192
8.3.1Incident Clocking192
8.3.2Embedded Clock192
9.Design Methodologies194
9.1Timings195
9.1.1Worst-Case Timing Spreadsheet196
9.1.2Statistical Spreadsheets198
9.2Timing Metrics, Signal Quality Metrics, and Test Loads200
9.2.1Voltage Reference Uncertainty200
9.2.2Simulation Reference Loads202
9.2.3Flight Time206
9.2.4Flight-Time Skew207
9.2.5Signal Integrity209
9.3Design Optimization210
9.3.1Paper Analysis211
9.3.2Routing Study212
9.4Sensitivity Analysis215
9.4.1Initial Trend and Significance Analysis215
9.4.2Ordered Parameter Sweeps221
9.4.3Phase 1 Solution Space224
9.4.4Phase 2 Solution Space225
9.4.5Phase 3 Solution Space228
9.5Design Guidelines229
9.6Extraction230
9.7General Rules of Thumb to Follow When Designing a System230
10.Radiated Emissions Compliance and System Noise Minimization232
10.1FCC Radiated Emission Specifications233
10.2Physical Mechanisms of Radiation233
10.2.1Differential-Mode Radiation234
10.2.2Common-Mode Radiation241
10.2.3Wave Impedance245
10.3Decoupling and Choking246
10.3.1High-Frequency Decoupling at the System Level248
10.3.2Choking Cables and Localized Power and Ground Planes253
10.3.3Low-Frequency Decoupling and Ground Isolation261
10.4Additional PCB Design Criteria, Package Considerations, and Pin-Outs263
10.4.1Placement of High-Speed Components and Traces263
10.4.2Crosstalk263
10.4.3Pin Assignments and Package Choice264
10.5Enclosure (Chassis) Considerations265
10.5.1Shielding Basics265
10.5.2Apertures267
10.5.3Resonances272
10.6Spread Spectrum Clocking273
11.High-Speed Measurement Techniques276
11.1Digital Oscilloscopes276
11.1.1Bandwidth277
11.1.2Sampling278
11.1.3Other Effects281
11.1.4Statistics283
11.2Time-Domain Reflectometry283
11.2.1TDR Theory284
11.2.2Measurement Factors287
11.3TDR Accuracy289
11.3.1Launch Parasitics290
11.3.2Probe Types292
11.3.3Reflections293
11.3.4Interface Transmission Loss293
11.3.5Cable Loss294
11.3.6Amplitude Offset Error294
11.4Impedance Measurement295
11.4.1Accurate Characterization of Impedance295
11.4.2Measurement Region in TDR Impedance Profile297
11.5Odd- and Even-Mode Impedance299
11.6Crosstalk Noise299
11.7Propagation Velocity300
11.7.1Length Difference Method301
11.7.2Y-Intercept Method301
11.7.3TDT Method302
11.8Vector Network Analyzer303
11.8.1Introduction to S Parameters304
11.8.2Equipment305
11.8.3One-Port Measurements (Z[subscript o],L,C)305
11.8.4Two-Port Measurements (T[subscript d], Attenuation, Crosstalk)310
11.8.5Calibration314
11.8.6Calibration for One-Port Measurements315
11.8.7Calibration for Two-Port Measurements316
11.8.8Calibration Verification316
Appendix AAlternative Characteristic Impedance Formulas318
A.1Microstrip318
A.2Symmetric Stripline319
A.3Offset Stripline319
Appendix BGTL Current-Mode Analysis321
B.1Basic GTL Operation321
B.2GTL Transitions When a Middle Agent Is Driving323
B.3GTL Transitions When an End Agent With a Termination Is Driving325
B.4Transitions When There is a Pull-Up at the Middle Agent327
Appendix CFrequency-Domain Components in a Digital Signal329
Appendix DUseful S-Parameter Conversions332
D.1ABCD, Z, and Y Parameters332
D.2Normalizing the S Matrix to a Different Characteristic Impedance335
D.3Derivation of the Formulas Used to Extract the Mutual Inductance and Capacitance from a Short Structure Using S[subscript 21] Measurements336
D.4Derivation of the Formula to Extract Skin Effect Resistance from a Transmission Line337
Appendix EDefinition of the Decibel338
Appendix FFCC Emission Limits340
Bibliography342
Index345

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