Compact MOSFET Models for VLSI Design / Edition 1

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Practicing designers, students, and educators in the semiconductor field face an ever expanding portfolio of MOSFET models. In Compact MOSFET Models for VLSI Design , A.B. Bhattacharyya presents a unified perspective on the topic, allowing the practitioner to view and interpret device phenomena concurrently using different modeling strategies. Readers will learn to link device physics with model parameters, helping to close the gap between device understanding and its use for optimal circuit performance. Bhattacharyya also lays bare the core physical concepts that will drive the future of VLSI development, allowing readers to stay ahead of the curve, despite the relentless evolution of new models.

  • Adopts a unified approach to guide students through the confusing array of MOSFET models
  • Links MOS physics to device models to prepare practitioners for real-world design activities
  • Helps fabless designers bridge the gap with off-site foundries
  • Features rich coverage of:
    • quantum mechanical related phenomena
    • Si-Ge strained-Silicon substrate
    • non-classical structures such as Double Gate MOSFETs
  • Presents topics that will prepare readers for long-term developments in the field
  • Includes solutions in every chapter
  • Can be tailored for use among students and professionals of many levels
  • Comes with MATLAB code downloads for independent practice and advanced study

This book is essential for students specializing in VLSI Design and indispensible for design professionals in the microelectronics and VLSI industries. Written to serve a number of experience levels, it can be used either as a course textbook or practitioner’s reference.

Access the MATLAB code, solution manual, and lecture materials at the companion website:

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Product Details

  • ISBN-13: 9780470823422
  • Publisher: Wiley
  • Publication date: 4/13/2009
  • Edition number: 1
  • Pages: 512
  • Product dimensions: 6.80 (w) x 9.80 (h) x 1.10 (d)

Meet the Author

A. B. Bhattacharyya is an Emeritus Professor at Jaypee Institute of Information Technology and has been involved in research in the area of microelectronics technology, device modeling and CMOS analog design for about 40 years. His current research interest are nanoscale CMOS Design and VLSI interconnect modeling. He has taught in VLSI subject areas for over 30 years, supervising over 30 Phd students. He was formerly a Professor at the Centre for Applied Research in Electronics, Indian Institute of Technology, Delhi, where he was also Dean of Industrial Research Development and Coordinator of the university's microelectronics program for 25 years. Bhattacharyya has published 150 papers in major journals and 40 conference papers, and has conducted tutorials at IEEE VLSI conferences. He is a Fellow at the Indian National Academy of Sciences, a Founder Fellow of the Indian National Academy of Engineering, and a Fellow at the Institute of Electronics and Telecommunication Engineering (India). National awards include Vikram Sarabhai, Vasvik, Khosla and S.N.Mitra Memorial Awards. Visiting assignments include University of Southampton, University of Rochester, University of California, Los Angeles, University of Twente, (Netherlands), University Pierre and Marie Curie (Paris), and the Moscow Power Institute.

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Table of Contents



List of Symbols.

1 Semiconductor Physics Review for MOSFET Modeling.

1.1 Introduction.

1.2 Crystal Planes.

1.3 Band Theory of Semiconductors.

1.4 Carrier Statistics.

1.5 Carrier Generation and Recombination.

1.6 Carrier Scattering.

1.7 Contacts and Interfaces.

1.8 Strained Silicon.

1.9 Basic Semiconductor Equations.

1.10 Compact MOSFET Models.

1.11 The pn Junction Diode.

1.12 Tunneling Through Potential Barrier.


2 Ideal Metal Oxide Semiconductor Capacitor.

2.1 Physical Structure and Energy Band Diagram.

2.2 Modes of Operation of MOS Capacitors.

2.3 Electric Field and Potential Distributions.

2.4 Potential Balance.

2.4.1 An Explicit Relation of φs with VGB.

2.5 Inversion Layer Thickness.

2.6 Threshold Voltage.

2.7 Small Signal Capacitance.

2.8 Three Terminal Ideal MOS Structures.


3 Non-ideal and Non-classical MOS Capacitors.

3.1 Introduction.

3.2 Flat-Band Voltage.

.2.2 Oxide Charges.

3.3 Inhomogeneous Substrate.

3.4 Polysilicon Depletion Effect.

3.5 Non-classical MOS Structures.

3.6 MOS Capacitor With Stacked Gate.


4 Long Channel MOS Transistor.

4.1 Introduction.

4.2 Layout and Cross-Section of Physical Structure.

4.3 Static Drain Current Model.

4.4 Threshold Voltage (VT ) Based Model.

4.5 Memelink–Wallinga Graphical Model.

4.6 Channel Length Modulation.

4.6.1 Early Voltage.

4.7 Channel Potential and Field Distribution Along Channel.

4.8 Carrier Transit Time.

4.9 EKV Drain Current Model.

4.10 ACM and BSIM5 Models.

4.11 PSP Model.

4.12 HiSIM (Hiroshima University STARC IGFET Model) Model.

4.13 Benchmark Tests for Compact DC Models.


5 The Scaled MOS Transistor.

5.1 Introduction.

5.2 Classical Scaling Laws.

5.3 Lateral Field Gradient.

5.4 Narrow and Inverse Width Effects.

5.5 Reverse Short Channel Effect.

5.6 Carrier Mobility Reduction.

5.7 Velocity Overshoot.

5.8 Channel Length Modulation: A Pseudo-2-D Analysis.

5.9 Series Resistance Effect on Drain Current.

5.10 Polydepletion Effect on Drain Current.

5.11 Impact Ionization in High Field Region.

5.12 Channel Punch-Through.

5.13 Empirical Alpha Power MOSFET Model.

5.13.1 Physical Interpretation of the Alpha Power Model.


6 Quasistatic, Non-quasistatic, and Noise Models.

6.1 Introduction.

6.2 Quasistatic Approximation.

6.3 Terminal Charge Evaluation.

6.4 Quasistatic Intrinsic Small Signal Model.

6.5 Extrinsic Capacitances.

6.6 Non-quasistatic (NQS) Models.

6.7 Noise Models.


7 Quantum Phenomena in MOS Transistors.

7.1 Introduction.

7.2 Carrier Energy Quantization in MOS Capacitor.

7.3 2-D Density of States.

7.4 Electron Concentration Distribution.

7.5 Approximate Methods.

7.6 Quantization Correction in Compact MOSFET Models.

7.7 Quantum Tunneling.

7.8 Gate Current Density.

7.9 Compact Gate Current Models.

7.10 Gate Induced Drain Leakage (GIDL).


8 Non-classical MOSFET Structures.

8.1 Introduction.

8.2 Non-classical MOSFET Structures.

8.3 Double Gate MOSFET Models.


Appendix A: Expression for Electric Field and Potential Variation in the Semiconductor Space Charge under the Gate.

Appendix B: Features of Select Compact MOSFET Models.

Appendix C: PSP Two-point Collocation Method.


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