Component Design by Example: A Step-by-Step Process Using VHDL with UART as Vehicle

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Product Details

  • ISBN-13: 9780970539403
  • Publisher: VhdlCohen Publishing
  • Publication date: 11/28/2000
  • Pages: 284

Table of Contents


FOREWORD..........IX
PREFACE..........XI
ABOUT THE DISK..........XV
ACKNOWLEDGEMENTS..........XVII
ABOUT THE AUTHOR..........XIX
DISCLAIMER..........XX
1 OVERVIEW..........
1
1.1 COMPONENT DESIGN PROCESS..........2
2 REQUIREMENT SPECIFICATION..........7
2.1 LANGUAGE..........8
2.2 UART REQUIREMENT SPECIFICATION..........11
1.0 SCOPE..........12
  1.1 SCOPE..........12
  1.2 PURPOSE..........12
  1.3 CLASSIFICATION..........12
2.0 DEFINITIONS..........12
  2.1 ASYNCHRONOUS TRANSMISSION..........12
  2.2 BAUD RATE..........12
  2.3 DTE..........12
  2.4 DCE..........12
  2.5 FRAMING ERROR..........12
  2.6 OVERRUN ERROR..........13
  2.7 PARITY..........13
  2.8 START BIT..........13
  2.9 STOP BIT..........13
  2.10 SYNCHRONOUS TRANSMISSION..........13
  2.11 UNDERRUN ERROR..........13
  2.12 WORD (WITH UART)..........13
3.0 APPLICABLE DOCUMENTS..........14
  3.1 GOVERNMENT DOCUMENTS..........14
  3.2 NON-GOVERNMENT DOCUMENTS..........14
  3.3 EXECUTABLE SPECIFICATIONS..........14
4.0 ARCHITECTURAL OVERVIEW..........14
  4.1 INTRODUCTION..........14
  4.2 SYSTEM APPLICATION..........15
5.0 PHYSICAL LAYER..........17
  5.1 INTERFACE PORT DESCRIPTION..........17
6.0 PROTOCOL LAYER..........23
7.0 ROBUSTNESS..........24
  7.1 ERROR DETECTION..........24
8.0 HARDWARE AND SOFTWARE..........24
  8.1 FIXED PARAMETERIZATION..........24
  8.2 SOFTWARE INTERFACES..........25
  8.3 MODES OF OPERATION..........30
9.0 PERFORMANCE..........30
  9.1 FREQUENCY..........30
  9.2 POWER DISSIPATION..........30
  9.3 ENVIRONMENTAL..........30
  9.4 TECHNOLOGY..........30
10.0 TESTABILITY..........30
11.0 MECHANICAL..........30

3 ARCHITECTURAL PLAN..........31
1.0 SCOPE..........33
  1.1 SCOPE..........33
  1.2 PURPOSE..........33
  1.3 CLASSIFICATION..........33
2.0 DEFINITIONS..........33
3.0 APPLICABLE DOCUMENTS..........33
4.0 ARCHITECTURAL OVERVIEW..........34
  4.1 CPU SUBBLOCK..........34
  4.2 RECEIVER SUBBLOCK..........34
  4.3 TRANSMIT SUBBLOCK..........35
  4.4 CLOCK SUBBLOCK..........35
5.0 PHYSICAL LAYER..........36
6.0 PROTOCOL LAYER..........37
7.0 ROBUSTNESS..........37
8.0 HARDWARE AND SOFTWARE..........37
  8.1 FIXED PARAMETERIZATION..........37
  8.2 SOTWARE INTERFACES..........37
9.0 PERFORMANCE..........37
10.0 TESTABILITY..........37
11.0 DESIGN TOOLS..........38

4 VERIFICATION PLAN..........39
4.1 METHODOLOGIES..........40
  4.1.1 What is a Verification Plan..........40
  4.1.2 Why a Verification Plan..........40
  4.1.3 Verification Languages..........42
4.2 VERIFICATION PLAN..........46
1.SCOPE..........47
  1.1 SCOPE..........47
  1.2 PURPOSE..........47
  1.3 CLASSIFICATION..........47
2.0 DEFINTIONS..........47
3.APPLICABLE DOCUMENTS..........48
  3.1 GOVERNEMENT DOCUMENTS..........48
  3.2 NON-GOVERNEMENT DOCUMENTS..........48
  3.3 EXECUTABLE SPECIFICATIONS..........48
  3.4 REFERENCE SOURCES..........48
4.COMPLIANCE PLAN..........49
  4.1 FEATURE EXTRACTION AND TEST STRATEGY..........49
  4.2 TESTBENCH ARCHITECTURE..........60
  4.3 VERIFIER..........69
5.DESIGN TOOLS..........72

5 DESIGN AND SYNTHESIS..........73
5.1 RTL DESIGN..........73
  5.1.1 CPU Interface (CpuIf) Subblock Design..........74
  CPUIF.VHD..........83
  5.1.2 Clock Control..........90
  CLKCNTRL.VHD..........92
  5.1.3 Receiver Subblock (rcvsublk)..........94
  RCVSUBLK.VHD..........97
  RECEIVER.VHD..........100
  FIFO.VHD..........103
  5.1.4 Transmit Subblock (xmitsublk)..........106
  5.1.5 UART Model..........108
  XMITSUBLK.VHD..........109
  TRANSMITTER.VHD..........112
  UART.VHD..........115
  5.1.6 Compilation..........120
  5.1.7 Synthesis..........120
  5.1.8 Layout..........124
  5.1.9 Area Statistics..........127
6 DESIGN VERIFICATION..........129
6.1 OVERVIEW..........130
6.2 PARSER PACKAGE..........130
  PARSER_PB.VHD..........133
6.3 CLIENT MODEL..........142
  UART_CLIENTRNDM.VHD..........145
  RCV_CLIENT.VHD..........150
6.4 SERVER..........152
  UART_SERVER.VHD..........153
  RCV_SERVER.VHD..........157
  FIFO_SERVER.VHD..........160
  FIFO_TB.VHD..........162
6.5 VERIFIER..........165
  6.5.1 ISSUES..........165
  6.5.2 Verifier Design Approach..........167
  6.5.3 Verifier Design..........171
  6.5.4 Top level Testbench..........175
  6.5.5 Configuration..........175
  VERIFPEEK.VHD..........176
  UART8_TB.VHD..........192
  UART_C.VHD..........198
  6.5.6 Definition of Scenarios (test cases)..........202
  COMMAND FILE: INSTR1.TXT..........202
  COMMAND FILE: CPU5TO15.TXT..........211
  COMMAND FILE: SW_RESET.TXT..........211
  COMMAND FILE: RCVINSTR.TXT..........214
  COMMAND FILE: RCV11TO15.TXT..........216
  6.5.7 Compilation Scripts..........217
  6.5.8 Simulation Results..........218
  6.5.9 Reading Text File into a Linked List …………………………227
7 DOCUMENTATION AND DELIVERY..........229
2.1 INTRODUCTION..........230
2.2 REFERENCE INFORMATION..........230
  2.2.1 Documented References..........230
  2.2.2 Terminology..........230
2.3 DELIVERABLE OVERVIEW..........230
2.4 DATA ORGANIZATION FOR THE PACKAGING OF DELIVERABLES..........233
2.5 DELIVERABLES DESCRIPTIONS..........238
  2.5.1 General Deliverables..........238
  2.5.2 Documentation Deliverables..........241
  2.5.3 Creation Guide..........243
  2.5.4 Logic Design Deliverables..........244
  2.5.5 Physical Design Deliverables..........244
  2.5.6 Design-for-Test and Manufacturing-Related Test Deliverables..........244
  2.5.7 Functional Verification Deliverables..........245
  2.5.8 Design Analysis Deliverables..........247
2.6 DESIGN STATUS AND RECOMMENDATIONS..........247
  2.6.1 Status..........247
  2.6.2 Suggested Work..........248
2.7 OPENMORE..........248
8 INTEGRATION OF COMPONENTS INTO DESIGNS..........259
8.1 APPLICATION OF UART INTO HIGHER LEVEL DESIGN..........260
  UART_LEVEL2.VHD..........261
8.2 HIGHER LEVEL COMPONENT EXTRACTION AND INTEGRATION..........264
  8.2.1 Motivation for change..........264
  8.2.2 Related Industry Trends..........265
  8.2.3 Types of IP Cores..........267
  8.2.4 Reuse Automation through High-Level Synthesis..........268
  8.2.5 IP-Centric Synthesis Methodology..........269
  8.2.6 Summary and Recommendation..........270
9 REFLECTIONS..........273
9.1 REQUIREMENTS..........273
  9.1.1 Realities..........273
  9.1.2 System implications..........275
  9.1.3 Consistency..........276
9.2 DESIGN..........277
9.3 VERIFICATION..........278
  9.3.1 Value of verifier...........279
  9.3.2 Code coverage..........279
  9.3.3 Debugger/LINTing..........280
  9.3.4 When is design fully verified..........280
  9.3.5 Text Command Files..........280
  9.3.6 Review of testplan against verifier implementation..........280
9.4 Summary and Conclusions..........281
INDEX..........283
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Foreword


When Ben first asked me if I would be interested in reviewing his latest book, I was
dually thrilled; once for the opportunity to contribute to the subject matter, second
because it meant that Ben was taking on some new issues. In my many years with
Synplicity â , I have had the opportunity to read or review many books. Of those, very
few I appreciated enough to recommend. Two of Ben's earlier books, VHDL Coding
Styles and Methodologies and VHDL Answers to Frequently Asked Questions are
truly the best of the lot. They have long been on my technical recommendation list. Ben
has an academic knowledge of the VHDL language, but utilizes that information with a
practitioner’s sense of reason. Both of these works are targeted toward the designer
who utilizes VHDL. He fills these books with tips and recommendations, explanations
as to why decisions are made and many references for further reading. What we gain
from these books are a practical guide to applying VHDL with consideration for both
the circuits to be implemented as well as the tools that you will used to create and verify
the designs. I was anticipating that this new work would be similar in approach.

In Component Design by Example, Ben attacks the design reuse problem. This topic
is timely and important. The Electronic Design Automation community has spent the
most of the last decade foreshadowing the emergence and importance of design re-use
and "IP" to obtain the next level of productivity gains. It is only in recently that we have
seen more frequent occurrences of design reuse. In the past few years, our customers
have begun to utilize various sizes and complexities of IP. With our customers, we have
discussed, planned, pondered and solved various problems and futures for the
development and reuse of design data and modular design flows. Consequently, we
have observed that there is much design data that is reused, but only after significant
effort. Often this is because the module was not successfully designed with reuse in
mind. I suspect that many designers lacked resources and references broad enough to
be useful on the topic of design for reuse.

Ben has created a pragmatic and useful book on design for reuse. It is useful because it
brings lots of practical information and experience in one place. Useful because he
dares to go beyond just the implementation phases of design, (which is more frequently
addressed), and takes on the procedures from conception to specification and planning.
PLEASE DON'T DISMISS THESE SECTIONS! Too many projects get into too
much trouble down the line due to incomplete, ambiguous, or "undocumented"
specifications and inadequate planning. It seems obvious, yet so many designers think
of it as overhead that impedes progress.

Component Design by Example will be useful to any designer or design team. It may
improve efficiency and improve products, or create disagreement in approach. My
hope is it will stimulate discussion. I expect it will be the foundation for a future filled
with IP. Read this before your next project. Then reread it afterward. You will
benefit both times.
Andrew R. Dauman
Vice-President of Corporate Applications
Synplicity, Inc.
Sunnyvale, CA
September 28, 2000

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