Computer Architecture: A Quantitative Approach, Second Edition / Edition 2

Computer Architecture: A Quantitative Approach, Second Edition / Edition 2

4.3 3
by John L. Hennessy, David A. Patterson, John L. Hennessy
     
 

"Once in a great while, a landmark computer-science book is published. Computer Architecture: A Quantitative Approach, Second Edition, is such a book. In an era of fluff computer books that are, quite properly, remaindered within weeks of publication, this book will stand the test of time, becoming lovingly dog-eared in the hands of anyone who designs

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Overview

"Once in a great while, a landmark computer-science book is published. Computer Architecture: A Quantitative Approach, Second Edition, is such a book. In an era of fluff computer books that are, quite properly, remaindered within weeks of publication, this book will stand the test of time, becoming lovingly dog-eared in the hands of anyone who designs computers or has concerns about the performance of computer programs." - Robert Bernecky, Dr. Dobb's Journal, April 1998


Computer Architecture: A Quantitative Approach was the first book to focus on computer architecture as a modern science. Its publication in 1990 inspired a new approach to studying and understanding computer design. Now, the second edition explores the next generation of architectures and design techniques with view to the future.



A basis for modern computer architecture

As the authors explain in their preface to the Second Edition, computer architecture itself has undergone significant change since 1990. Concentrating on currently predominant and emerging commercial systems, the Hennessy and Patterson have prepared entirely new chapters covering additional advanced topics:

  • Advanced Pipelining: A new chapter emphasizes superscalar and multiple issues.
  • Networks: A new chapter examines in depth the design issues for small and large shared-memory multiprocessors.
  • Storage Systems: Expanded presentation includes coverage of I/O performance measures.
  • Memory: Expanded coverage of caches and memory-hierarchy design addresses contemporary design issues.
  • Examples and Exercises: Completely revised on current architectures such as MIPS R4000, Intel 80x86 and Pentium, PowerPC, and HP PA-RISC.



Distinctive presentation

This book continues the style of the first edition, with revised sections on Fallacies and Pitfalls, Putting It All Together and Historical Perspective, and contains entirely new sections on Crosscutting Issues. The focus on fundamental techniques for designing real machines and the attention to maximizing cost/performance are crucial to both students and working professionals. Anyone involved in building computers, from palmtops to supercomputers, will profit from the expertise offered by Hennessy and Patterson.

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Product Details

ISBN-13:
9781558603295
Publisher:
Elsevier Science & Technology Books
Publication date:
08/28/1995
Edition description:
Older Edition
Pages:
1000
Product dimensions:
7.81(w) x 9.57(h) x 2.10(d)

Meet the Author


David A. Patterson (University of California at Berkeley) has been teaching computer architecture at the University of California, Berkeley, since joining the faculty in 1977, and he holds the Pardee Chair of Computer Science. His teaching has been honored by the ACM, the IEEE, and the University of California. Patterson has also received the 1995 IEEE Technical Achievement Award for contributions to RISC and the 1999 IEEE Reynold B. Johnson Information Storage Award for contributions to RAID. He is a member of the National Academy of Engineering and is a fellow of both the ACM and the IEEE. In the past, he has been chair of the CS division in the EECS department at Berkeley, the ACM SIG in computer architecture, and the Computing Research Association.

At Berkeley, Patterson led the design and implementation of RISC I, likely the first VLSI Reduced Instruction Set Computer. This research became the foundation of the SPARC architecture, currently used by Sun Microsystems, Fujitsu, and others. He was also a leader of the Redundant Arrays of Inexpensive Disks (RAID) project, which led to high-performance storage systems from many companies. These projects earned three dissertation awards from the ACM. His current research interests are in building novel microprocessors using Intelligent DRAM (IRAM) and he currently consults for Sun, where he holds the title of Chief Scientist of the Network Attached Storage Division.

John L. Hennessy teaches computer architecture at Stanford University, where he has been a member of the faculty since 1977. He is currently Dean of the School of Engineering and the Frederick Emmons Terman Professor of Engineering. Hennessy is a fellowof the IEEE and ACM, a member of the National Academy of Engineering, and a fellow of the American Academy of Arts and Sciences. He received the 1994 IEEE Piore Award for his contributions to the development of RISC technology.

Hennessy's original research group at Stanford developed several of the techniques now in commercial use for optimizing compilers. In 1981, he started the MIPS project at Stanford with a handful of graduate students. After completing the project in 1984, he took a one-year leave from the university to co-found MIPS Computer Systems, which developed one of the first commercial RISC microprocessors. After being acquired by Silicon Graphics in 1991, MIPS Technologies became an independent company in 1998, focusing on microprocessors for the embedded marketplace. As of 1998, over 100 million MIPS microprocessors have been shipped in devices ranging from video games and palmtop computers to laser printers and network switches. Hennessy's recent research at Stanford focuses on the area of designing and exploiting multiprocessors. Recently, he has been involved in the development of the DASH multiprocessor architecture, the first distributed shared-memory multiprocessors supporting cache coherency, and the basis for several commercial multiprocessor designs.

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Table of Contents

Foreword
Preface
Acknowledgments
1Fundamentals of Computer Design
2Instruction Set Principles and Examples
3Pipelining
4Advanced Pipelining and Instruction-Level Parallelism
5Memory-Hierarchy Design
6Storage Systems
7Interconnection Networks
8Multiprocessors
Appendix A: Computer Arithmetic
Appendix B: Vector Processors
Appendix C: Survey of RISC Architectures
Appendix D: An Alternative to RISC: The Intel 80x86
Appendix E: Implementing Coherence Protocols
References
Index

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