Computer Architecture: Pipelined And Parallel Processor Design / Edition 1

Computer Architecture: Pipelined And Parallel Processor Design / Edition 1

by Michael J. Flynn
     
 

ISBN-10: 0867202041

ISBN-13: 9780867202045

Pub. Date: 05/10/1995

Publisher: Jones & Bartlett Learning

Computer Architecture: Pipeline and Parallel Processor Design was designed for a graduate level course on computer architecture and organization. The book's content, especially the last half of the book, represents the most advanced material that a typical graduate student studies before directly encountering the design process. The text avoids extensive

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Overview

Computer Architecture: Pipeline and Parallel Processor Design was designed for a graduate level course on computer architecture and organization. The book's content, especially the last half of the book, represents the most advanced material that a typical graduate student studies before directly encountering the design process. The text avoids extensive compendiums of current features of various processors or technologies, just as it stresses concepts that underlie these processor designs. It abstracts the essential elements of processor design and emphasizes a design methodology including: design concepts, design target data, and evaluation tools, especially those using basic probability theory and simple queuing theory.

Product Details

ISBN-13:
9780867202045
Publisher:
Jones & Bartlett Learning
Publication date:
05/10/1995
Edition description:
1E
Pages:
808
Product dimensions:
7.24(w) x 10.28(h) x 1.85(d)

Table of Contents

Preface
Acknowledgments
1Architecture and Machines1
2Time, Area, and Instruction Sets63
3Data: How Programs Behave141
4Pipelined Processor Design181
5Cache Memory265
6Memory System Design345
7Concurrent Processors425
8Shared Memory Multiprocessors511
9I/O and the Storage Hierarchy599
10Processor Studies663
Appendix A DTMR Cache Miss Rates719
Appendix B SPECmark vs. DTMR Cache Performance741
Appendix C Modeling System Effects in Caches743
Appendix D New DRAM Technologies747
Appendix E M/G/1 Queues751
Appendix F Some Details on Bus-Based Protocols755
Bibliography765
Index782

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