Computer Organization and Design: The Hardware/Software Interface / Edition 4

Computer Organization and Design: The Hardware/Software Interface / Edition 4

by David A. Patterson, John L. Hennessy
     
 

ISBN-10: 0123744938

ISBN-13: 9780123744937

Pub. Date: 10/27/2008

Publisher: Elsevier Science

Computer Organization and Design

The Hardware/Software Interface

David A. Patterson and John L. Hennessy

Patterson and Hennessy have greatly improved what was already the gold standard of textbooks. In the rapidly-evolving field of computer architecture, they have woven an impressive number of recent case studies and contemporary issues into

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Overview

Computer Organization and Design

The Hardware/Software Interface

David A. Patterson and John L. Hennessy

Patterson and Hennessy have greatly improved what was already the gold standard of textbooks. In the rapidly-evolving field of computer architecture, they have woven an impressive number of recent case studies and contemporary issues into a framework of time-tested fundamentals.—Fred Chong, University of California, Santa Barbara

The new coverage of multiprocessors and parallelism lives up to the standards of this well-written classic. It provides well-motivated, gentle introductions to the new topics, as well as many details and examples drawn from current hardware.—John Greiner, Rice University

The best-selling computer organization book is thoroughly updated to provide a new focus on the revolutionary change taking place in industry today: the switch from uniprocessor to multicore microprocessors. This new emphasis on parallelism is supported by updates reflecting the newest technologies, with examples highlighting the latest processor designs and benchmarking standards. As with previous editions, a MIPS processor is the core used to present the fundamentals of hardware technologies, assembly language, computer arithmetic, pipelining, memory hierarchies and I/O. Sections on the ARM and x86 architectures are also included.

A companion CD provides a toolkit of simulators and compilers along with tutorials for using them, as well as advanced content for further study and a search utility for finding content on the CD and in the printed text.

Fourth Edition Features:

  • Covers the revolutionary change from sequential to parallel computing, with a new chapter on parallelism and sections in every chapter highlighting parallel hardware and software topics.
  • Includes a new appendix by the Chief Scientist and the Director of Architecture of NVIDIA covering the emergence and importance of the modern GPU, describing in detail for the first time the highly parallel, highly multithreaded multiprocessor optimized for visual computing.
  • Describes a novel approach to measuring multicore performance—the "Roofline model"—with benchmarks and analysis for the AMD Opteron X4, Intel Xeon 5000, Sun UltraSPARC T2, and IBM Cell.
  • Includes new content on Flash memory and Virtual Machines.
  • Provides a large, stimulating set of new exercises, covering almost 200 pages.
  • Features the AMD Opteron X4 and Intel Nehalem as real-world examples throughout the book.
  • Updates all processor performance examples using the SPEC CPU2006 suite.

Online support materials for this book are available at textbooks.elsevier.com/9780123744937

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Product Details

ISBN-13:
9780123744937
Publisher:
Elsevier Science
Publication date:
10/27/2008
Series:
Morgan Kaufmann Series in Computer Architecture and Design Series
Edition description:
Older Edition
Pages:
912
Product dimensions:
7.50(w) x 9.20(h) x 1.60(d)

Table of Contents


Preface     xi
Computer Abstractions and Technology     2
Introduction     3
Below Your Program     11
Under the Covers     15
Real Stuff: Manufacturing Pentium 4 Chips     28
Fallacies and Pitfalls     33
Concluding Remarks     35
Historical Perspective and Further Reading     36
Exercises     36
Computers in the Real World: Information Technology for the 4 Billion without IT     44
Instructions: Language of the Computer     46
Introduction     48
Operations of the Computer Hardware     49
Operands of the Computer Hardware     52
Representing Instructions in the Computer     60
Logical Operations     68
Instructions for Making Decisions     72
Supporting Procedures in Computer Hardware     79
Communicating with People     90
MIPS Addressing for 32-Bit Immediates and Addresses     95
Translating and Starting a Program     106
How Compilers Optimize     116
How Compilers Work: An Introduction     121
A C Sort Example to Put It All Together     121
Implementing an Object-Oriented Language     130
Arrays versus Pointers     130
Real Stuff: IA-32 Instructions     134
Fallacies and Pitfalls     143
Concluding Remarks     145
Historical Perspective and Further Reading     147
Exercises     147
Computers in the Real World: Helping Save Our Environment with Data     156
Arithmetic for Computers     158
Introduction     160
Signed and Unsigned Numbers     160
Addition and Subtraction     170
Multiplication     176
Division     183
Floating Point     189
Real Stuff: Floating Point in the IA-32     217
Fallacies and Pitfalls     220
Concluding Remarks     225
Historical Perspective and Further Reading     229
Exercises     229
Computers in the Real World: Reconstructing the Ancient World     236
Assessing and Understanding Performance     238
Introduction     240
CPU Performance and Its Factors     246
Evaluating Performance     254
Real Stuff: Two SPEC Benchmarks and the Performance of Recent Intel Processors     259
Fallacies and Pitfalls     266
Concluding Remarks     270
Historical Perspective and Further Reading     272
Exercises     272
Computers in the Real World: Moving People Faster and More Safely     280
The Processor: Datapath and Control     282
Introduction     284
Logic Design Conventions     289
Building a Datapath     292
A Simple Implementation Scheme     300
A Multicycle Implementation     318
Exceptions     340
Microprogramming: Simplifying Control Design     346
An Introduction to Digital Design Using a Hardware Design Language     346
Real Stuff: The Organization of Recent Pentium Implementations     347
Fallacies and Pitfalls     350
Concluding Remarks     352
Historical Perspective and Further Reading     353
Exercises     354
Computers in the Real World: Empowering the Disabled     366
Enhancing Performance with Pipelining     368
An Overview of Pipelining     370
A Pipelined Datapath     384
Pipelined Control     399
Data Hazards and Forwarding     402
Data Hazards and Stalls     413
Control Hazards     416
Using a Hardware Description Language to Describe and Model a Pipeline     426
Exceptions     427
Advanced Pipelining: Extracting More Performance     432
Real Stuff: The Pentium 4 Pipeline     448
Fallacies and Pitfalls     451
Concluding Remarks     452
Historical Perspective and Further Reading     454
Exercises     454
Computers in the Real World: Mass Communication without Gatekeepers     464
Large and Fast: Exploiting Memory Hierarchy     466
Introduction     468
The Basics of Caches     473
Measuring and Improving Cache Performance     492
Virtual Memory     511
A Common Framework for Memory Hierarchies     538
Real Stuff: The Pentium P4 and the AMD Opteron Memory Hierarchies     546
Fallacies and Pitfalls     550
Concluding Remarks     552
Historical Perspective and Further Reading     555
Exercises     555
Computers in the Real World: Saving the World's Art Treasures     562
Storage, Networks, and Other Peripherals     564
Introduction     566
Disk Storage and Dependability     569
Networks     580
Buses and Other Connections between Processors, Memory, and I/O Devices     581
Interfacing I/O Devices to the Processor, Memory, and Operating System     588
I/O Performance Measures: Examples from Disk and File Systems     597
Designing an I/O System     600
Real Stuff: A Digital Camera     603
Fallacies and Pitfalls     606
Concluding Remarks     609
Historical Perspective and Further Reading     611
Exercises     611
Computers in the Real World: Saving Lives through Better Diagnosis     622
Multiprocessors and Clusters     2
Introduction     4
Programming Multiprocessors     8
Multiprocessors Connected by a Single Bus     11
Multiprocessors Connected by a Network     21
Clusters     25
Network Topologies     27
Multiprocessors Inside a Chip and Multithreading     30
Real Stuff: The Google Cluster of PCs     34
Fallacies and Pitfalls     39
Concluding Remarks     42
Historical Perspective and Further Reading     47
Exercises     55
Appendices
Assemblers, Linkers, and the SPIM Simulator     2
Introduction      3
Assemblers     10
Linkers     18
Loading     19
Memory Usage     20
Procedure Call Convention     22
Exceptions and Interrupts     33
Input and Output     37
SPIM     40
MIPS R2000 Assembly Language     44
Concluding Remarks     79
Exercises     80
The Basics of Logic Design     2
Introduction     3
Gates, Truth Tables, and Logic Equations     4
Combinational Logic     8
Using a Hardware Description Language     20
Constructing a Basic Arithmetic Logic Unit     26
Faster Addition: Carry Lookahead     38
Clocks     47
Memory Elements: Flip-Flops, Latches, and Registers     49
Memory Elements: SRAMs and DRAMs     57
Finite-State Machines     67
Timing Methodologies     72
Field Programmable Devices     77
Concluding Remarks     78
Exercises     79
Mapping Control to Hardware     2
Introduction     3
Implementing Combinational Control Units     4
Implementing Finite-State Machine Control      8
Implementing the Next-State Function with a Sequencer     21
Translating a Microprogram to Hardware     27
Concluding Remarks     31
Exercises     32
A Survey of RISC Architectures for Desktop, Server, and Embedded Computers     2
Introduction     3
Addressing Modes and Instruction Formats     5
Instructions: The MIPS Core Subset     9
Instructions: Multimedia Extensions of the Desktop/Server RISCs     16
Instructions: Digital Signal-Processing Extensions of the Embedded RISCs     19
Instructions: Common Extensions to MIPS Core     20
Instructions Unique to MIPS-64     25
Instructions Unique to Alpha     27
Instructions Unique to SPARC v.9     29
Instructions Unique to PowerPC     32
Instructions Unique to PA-RISC 2.0     34
Instructions Unique to ARM     36
Instructions Unique to Thumb     38
Instructions Unique to SuperH     39
Instructions Unique to M32R     40
Instructions Unique to MIPS-16     41
Concluding Remarks     43
Index     I-1
Glossary     G-1
Further Reading     FR-1

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