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Computer Organization and Design: The Hardware/Software Interface, Third Edition / Edition 3

Overview

This best selling text on computer organization has been thoroughly updated to reflect the newest technologies. Examples highlight the latest processor designs, benchmarking standards, languages and tools.

As with previous editions, a MIPs processor is the core used to present the fundamentals of hardware technologies at work in a computer system. The book presents an entire MIPS instruction set-instruction by instruction-the fundamentals of assembly language, computer arithmetic, pipelining, memory hierarchies and I/O.

A new aspect of the third edition is the explicit connection between program performance and CPU performance. The authors show how hardware and software components--such as the specific algorithm, programming language, compiler, ISA and processor implementation--impact program performance. Throughout the book a new feature focusing on program performance describes how to search for bottlenecks and improve performance in various parts of the system. The book digs deeper into the hardware/software interface, presenting a complete view of the function of the programming language and compiler--crucial for understanding computer organization. A CD provides a toolkit of simulators and compilers along with tutorials for using them.



For instructor resources click on the grey "companion site" button found on the right side of this page.
This new edition represents a major revision.
New to this edition:

* Entire Text has been updated to reflect new technology
* 70% new exercises.
* Includes a CD loaded with software, projects and exercises to support courses using a number of tools
* A new interior design presents defined terms in the margin for quick reference
* A new feature, "Understanding Program Performance" focuses on performance from the programmer's perspective
* Two sets of exercises and solutions, "For More Practice" and "In More Depth," are included on the CD
* "Check Yourself" questions help students check their understanding of major concepts
* "Computers In the Real World" feature illustrates the diversity of uses for information technology
*More detail below...

Patterson-Hennessey's new work offers the most current and comprehensive coverage of the topic and is the only book on the market to include RISC architectures. The book is intended to teach a broader audience the fundamentals of computing including programs, operating systems, and compilers.

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Editorial Reviews

From Barnes & Noble
The Barnes & Noble Review
Even today, to write great software, it helps to understand the underlying hardware. And if you’re a hardware architect, you’d better understand how your choices will impact developers. Computer Organization and Design, Third Edition will help software and hardware folks understand each other. The authors even provide separate learning paths for each audience.

Using the actual MIPS 32 architecture to ground their discussions in reality, David Patterson and John Hennessy illuminate computer arithmetic, pipelining, memory hierarchies, I/O, multiprocessing, clustering, and much more. Throughout, welcome “Fallacies and Pitfalls” sections clear up much of the misinformation that bedevils the field.

This edition’s been heavily updated, both for clarity and content. Especially worth noting: a stronger focus on the relationship between hardware and program performance, and a comparison of the Pentium 4 with AMD’s influential new Opteron. Bill Camarda

Bill Camarda is a consultant, writer, and web/multimedia content developer. His 15 books include Special Edition Using Word 2003 and Upgrading & Fixing Networks for Dummies, Second Edition.

Booknews
An introduction to the field for students in software and hardware design, emphasizing the relationships between software and hardware. Presents each idea from its first principles, adding complexity through a series of worked examples and solutions, with coverage of the MIPS instruction set, fundamentals of assembly language, computer arithmetic, pipelining, and memory hierarchies. Discusses design, performance, and significance of I/O systems, and emerging architectures of multiprocessor systems. Each chapter includes sections on examples (new to this edition), fallacies and pitfalls, and history of the field, plus exercises and key terms. Layout is attractive and readable. Assumes beginning courses in programming. Annotation c. by Book News, Inc., Portland, Or.
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Product Details

Meet the Author

David A. Patterson was the first in his family to graduate from college (1969 A.B UCLA), and he enjoyed it so much that he didn't stop until a PhD, (1976 UCLA). After 4 years developing a wafer-scale computer at Hughes Aircraft, he joined U.C. Berkeley in 1977. He spent 1979 at DEC working on the VAX minicomputer. He and colleagues later developed the Reduced Instruction Set Computer (RISC). By joining forces with IBM’s 801 and Stanford’s MIPS projects, RISC became widespread. In 1984 Sun Microsystems recruited him to start the SPARC architecture. In 1987, Patterson and colleagues wondered if tried building dependable storage systems from the new PC disks. This led to the popular Redundant Array of Inexpensive Disks (RAID). He spent 1989 working on the CM-5 supercomputer. Patterson and colleagues later tried building a supercomputer using standard desktop computers and switches. The resulting Network of Workstations (NOW) project led to cluster technology used by many startups. He is now working on the Recovery Oriented Computing (ROC) project. In the past, he served as Chair of Berkeley's CS Division, Chair and CRA. He is currently serving on the IT advisory committee to the U.S. President and has just been elected President of the ACM. All this resulted in 150 papers, 5 books, and the following honors, some shared with friends: election to the National Academy of Engineering; from the University of California: Outstanding Alumnus Award (UCLA Computer Science Department), McEntyre Award for Excellence in Teaching (Berkeley Computer Science), Distinguished Teaching Award (Berkeley); from ACM: fellow, SIGMOD Test of Time Award, Karlstrom Outstanding Educator Award; from IEEE: fellow, Johnson Information Storage Award, Undergraduate Teaching Award, Mulligan Education Medal, and von Neumann Medal.

John L. Hennessy is the president of Stanford University, where he has been a member of the faculty since 1977 in the departments of electrical engineering and computer science. Hennessy is a fellow of the IEEE and the ACM, a member of the National Academy of Engineering, the National Academy of Science, the American Academy of Arts and Sciences, and the Spanish Royal Academy of Engineering. He received the 2001 Eckert-Mauchly Award for his contributions to RISC technology, the 2001 Seymour Cray Computer Engineering Award, and shared the John von Neumann award in 2000 with David Patterson. After completing the project in 1984, he took a one-year leave from the university to co-found MIPS Computer Systems, which developed one of the first commercial RISC microprocessors. After being acquired by Silicon Graphics in 1991, MIPS Technologies became an independent company in 1998, focusing on microprocessors for the embedded marketplace. As of 2004, over 300 million MIPS microprocessors have been shipped in devices ranging from video games and palmtop computers to laser printers and network switches. Hennessy's more recent research at Stanford focuses on the area of designing and exploiting multiprocessors. He helped lead the design of the DASH multiprocessor architecture, the first distributed shared-memory multiprocessors supporting cache coherency, and the basis for several commercial multiprocessor designs, including the Silicon Graphics Origin multiprocessors. Since becoming president of Stanford, revising and updating this text and the more advanced Computer Architecture: A Quantitative Approach has become a primary form of recreation and relaxation.

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Table of Contents

1 Computer Abstractions and Technology
2 Instructions: Language of the Computer
3 Arithmetic for Computers
4 Assessing and Understanding Performance
5 The Processor: Datapath and Control
6 Enhancing Performance with Pipelining
7 Large and Fast: Exploiting Memory Hierarchy
8 Storage, Networks, and Other Peripherals
On the CD:
9 Multiprocessors
Appendix A: Assemblers, Linkers, and the Spim simulator
Appendix B: The Basics of Logic Design
Appendix C: Mapping Control to Hardware
Appendix D: A Survey of RISC Architectures for Desktop, Server, and Embedded Computers
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