Computer Organization and Design MIPS Edition: The Hardware/Software Interface

by David A. Patterson, John L. Hennessy

Overview

Computer Organization and Design: The Hardware/Software Interface, Sixth Edition, the leading, award-winning textbook from Patterson and Hennessy used by more than 40,000 students per year, continues to present the most comprehensive and readable introduction to this core computer science topic. Improvements to this new release include new sections in each chapter on Domain Specific Architectures (DSA) and updates on all real-world examples that keep it fresh and relevant for a new generation of students.

Product Details

ISBN-13:	9780128201091
Publisher:	Elsevier Science
Publication date:	11/20/2020
Series:	The Morgan Kaufmann Series in Computer Architecture and Design
Edition description:	6th ed.
Pages:	832
Product dimensions:	7.50(w) x 9.25(h) x (d)

About the Author

ACM named David A. Patterson a recipient of the 2017 ACM A.M. Turing Award for pioneering a systematic, quantitative approach to the design and evaluation of computer architectures with enduring impact on the microprocessor industry. David A. Patterson is the Pardee Chair of Computer Science, Emeritus at the University of California Berkeley. His teaching has been honored by the Distinguished Teaching Award from the University of California, the Karlstrom Award from ACM, and the Mulligan Education Medal and Undergraduate Teaching Award from IEEE. Patterson received the IEEE Technical Achievement Award and the ACM Eckert-Mauchly Award for contributions to RISC, and he shared the IEEE Johnson Information Storage Award for contributions to RAID. He also shared the IEEE John von Neumann Medal and the C & C Prize with John Hennessy. Like his co-author, Patterson is a Fellow of the American Academy of Arts and Sciences, the Computer History Museum, ACM, and IEEE, and he was elected to the National Academy of Engineering, the National Academy of Sciences, and the Silicon Valley Engineering Hall of Fame. He served on the Information Technology Advisory Committee to the U.S. President, as chair of the CS division in the Berkeley EECS department, as chair of the Computing Research Association, and as President of ACM. This record led to Distinguished Service Awards from ACM, CRA, and SIGARCH.

ACM named John L. Hennessy a recipient of the 2017 ACM A.M. Turing Award for pioneering a systematic, quantitative approach to the design and evaluation of computer architectures with enduring impact on the microprocessor industry. John L. Hennessy is a Professor of Electrical Engineering and Computer Science at Stanford University, where he has been a member of the faculty since 1977 and was, from 2000 to 2016, its tenth President. Prof. Hennessy is a Fellow of the IEEE and ACM; a member of the National Academy of Engineering, the National Academy of Science, and the American Philosophical Society; and a Fellow of the American Academy of Arts and Sciences. Among his many awards are the 2001 Eckert-Mauchly Award for his contributions to RISC technology, the 2001 Seymour Cray Computer Engineering Award, and the 2000 John von Neumann Award, which he shared with David Patterson. He has also received seven honorary doctorates.

Table of Contents

Preface xv

Chapter 1 Computer Abstractions and Technology 2

1.1 Introduction 3

1.2 Seven Great Ideas in Computer Architecture 10

1.3 Below Your Program 13

1.4 Under the Covers 16

1.5 Technologies for Building Processors and Memory 24

1.6 Performance 28

17 The Power Wall 40

1.8 The Sea Change: The Switch from Uniprocessors to Multiprocessors 43

1.9 Real Stuff: Benchmarking the Intel Core i7 46

1.10 Going Faster: Matrix Multiply in Python 49

1.11 Fallacies and Pitfalls 50

1.12 Concluding Remarks 53

1.13 Historical Perspective and Further Reading 55

1.14 Self-Study 55

1.15 Exercises 59

Chapter 2 Instructions: Language of the Computer 66

2.1 Introduction 68

2.2 Operations of the Computer Hardware 69

2.3 Operands of the Computer Hardware 72

2.4 Signed and Unsigned Numbers 79

2.5 Representing Instructions in the Computer 86

2.6 Logical Operations 93

2.7 Instructions for Making Decisions 96

2.8 Supporting Procedures in Computer Hardware 102

2.9 Communicating with People 112

2.10 MIPS Addressing for 32-Bit Immediates and Addresses 118

2.11 Parallelism and Instructions: Synchronization 127

2.12 Translating and Starting a Program 129

2.13 A C Sort Example to Put It All Together 138

2.14 Arrays versus Pointers 147

2.15 Advanced Material: Compiling C and Interpreting Java 151

2.16 Real Stuff: ARMv7 (32-bit) Instructions 151

2.17 Real Stuff: ARMv8 (64-bit) Instructions 155

2.18 Real Stuff: RISC-V Instructions 156

2.19 Real Stuff: x86 Instructions 157

2.20 Going Faster: Matrix Multiply in C 166

2.21 Fallacies and Pitfalls 167

2.22 Concluding Remarks 169

2.23 Historical Perspective and Further Reading 172

2.24 Self Study 172

2.25 Exercises 175

Chapter 3 Arithmetic for Computers 186

3.1 Introduction 188

3.2 Addition and Subtraction 188

3.3 Multiplication 193

3.4 Division 199

3.5 Floating Point 206

3.6 Parallelism and Computer Arithmetic: Subword Parallelism 232

3.7 Real Stuff: Streaming SIMD Extensions and Advanced Vector Extensions in x86 234

3.8 Going Faster: Subword Parallelism and Matrix Multiply 235

3.9 Fallacies and Pitfalls 237

3.10 Concluding Remarks 241

3.11 Historical Perspective and Further Reading 245

3.12 Self Study 245

3.13 Exercises 248

Chapter 4 The Processor 254

4.1 Introduction 256

4.2 Logic Design Conventions 260

4.3 Building a Datapath 263

4.4 A Simple Implementation Scheme 271

4.5 A Multicycle Implementation 284

4.6 An Overview of Pipelining 285

4.7 Pipelined Datapath and Control 298

4.8 Data Hazards: Forwarding versus Stalling 315

4.9 Control Hazards 328

4.10 Exceptions 337

4.11 Parallelism via Instructions 344

4.12 Putting It All Together: The Intel Core i7 6700 and ARM Cortex-A53 358

4.13 Going Faster: Instruction-Level Parallelism and Matrix Multiply 366

4.14 Advanced Topic: An Introduction to Digital Design Using a Hardware Design Language to Describe and Model a Pipeline and More Pipelining Illustrations 368

4.15 Fallacies and Pitfalls 369

4.16 Concluding Remarks 370

4.17 Historical Perspective and Further Reading 371

4.18 Self-Study 371

4.19 Exercises 372

Chapter 5 Large and Fast: Exploiting Memory Hierarchy 390

5.1 Introduction 392

5.2 Memory Technologies 396

5.3 The Basics of Caches 401

5.4 Measuring and Improving Cache Performance 416

5.5 Dependable Memory Hierarchy 436

5.6 Virtual Machines 442

5.7 Virtual Memory 446

5.8 A Common Framework for Memory Hierarchy 472

5.9 Using a Finite-State Machine to Control a Simple Cache 479

5.10 Parallelism and Memory Hierarchies: Cache Coherence 484

5.11 Parallelism and Memory Hierarchy: Redundant Arrays of Inexpensive Disks 488

5.12 Advanced Material: Implementing Cache Controllers 488

5.13 Real Stuff: The ARM Cortex-A8 and Intel Core i7 Memory Hierarchies 489

5.14 Going Faster: Cache Blocking and Matrix Multiply 494

5.15 Fallacies and Pitfalls 496

5.16 Concluding Remarks 500

5.17 Historical Perspective and Further Reading 501

5.18 Self-Study 501

5.19 Exercises 506

Chapter 6 Parallel Processors from Client to Cloud 524

6.1 Introduction 526

6.2 The Difficulty of Creating Parallel Processing Programs 528

6.3 SISD, MIMD, SIMD, SPMD, and Vector 533

6.4 Hardware Multithreading 540

6.5 Multicore and Other Shared Memory Multiprocessors 543

6.6 Introduction to Graphics Processing Units 548

6.7 Domain Specific Architectures 555

6.8 Clusters, Warehouse Scale Computers, and Other Message-Passing Multiprocessors 558

6.9 Introduction to Multiprocessor Network Topologies 563

6.10 Communicating to the Outside World: Cluster Networking 566

6.11 Multiprocessor Benchmarks and Performance Models 567

6.12 Real Stuff: Benchmarking the Google TPUv3 Supercomputer and an NVIDIA Volta GPU Cluster 577

6.13 Going Faster: Multiple Processors and Matrix Multiply 586

6.14 Fallacies and Pitfalls 589

6.15 Concluding Remarks 592

6.16 Historical Perspective and Further Reading 594

6.17 Self Study 594

6.18 Exercises 596

Appendices

A Assemblers, Linkers, and the SPIM Simulator A-610

A.1 Introduction A-611

A.2 Assemblers A-618

A.3 Linkers A-626

A.4 Loading A-627

A.5 Memory Usage A-628

A.6 Procedure Call Convention A-630

A.7 Exceptions and Interrupts A-641

A.8 Input and Output A-646

A.9 SPIM A-648

A.10 MIPS R2000 Assembly Language A-653

A.11 Concluding Remarks A-689

A.12 Exercises A-690

B The Basics of Logic Design B-692

B.1 Introduction B-693

B.2 Gates, Truth Tables, and Logic Equations B-694

B.3 Combinational Logic B-699

B.4 Using a Hardware Description Language B-710

B.5 Constructing a Basic Arithmetic Logic Unit B-716

B.6 Faster Addition: Carry Lookahead B-728

B.7 Clocks B-738

B.8 Memory Elements: Flip-Flops, Latches, and Registers B-740

B.9 Memory Elements: SRAMs and DRAMs B-748

B.10 Finite-State Machines B-757

B.11 Timing Methodologies B-762

B.12 Field Programmable Devices B-768

B.13 Concluding Remarks B-769

B.14 Exercises B-770

Index I-1

Online Content

C Graphics and Computing GPUs C-2

C.1 Introduction C-3

C.2 GPU System Architectures C-7

C.3 Programming GPUs C-12

C.4 Multithreaded Multiprocessor Architecture C-25

C.5 Parallel Memory System C-36

C.6 Floating Point Arithmetic C-41

C.7 Real Stuff: The NVTDIA GeForce 8800 C-46

C.8 Real Stuff: Mapping Applications to GPUs C-55

C.9 Fallacies and Pitfalls C-72

C.10 Concluding Remarks C-76

C.11 Historical Perspective and Further Reading C-77

D Mapping Control to Hardware D-2

D.1 Introduction D-3

D.2 Implementing Combinational Control Units D-4

D.3 Implementing Finite-State Machine Control D-8

D.4 Implementing the Next-State Function with a Sequencer D-22

D.5 Translating a Microprogram to Hardware D-28

D.6 Concluding Remarks D-32

D.7 Exercises D-33

E Survey of Instruction Set Architectures

E.1 Introduction E-3

E.2 A Survey of RISC Architecture for Desktop, Server, and Embedded Computers E-4

E.3 The Intel 80×86 E-30

E.4 The VAX Architecture E-50

E.5 The IBM 360/370 Architecture for Mainframe Computers E-69

E.6 Historical Perspective and References E-73

Glossary G-1

Further Reading FR-1

What People are Saying About This

From the Publisher

The market-leading title for computer organization courses, with state-of-the art content and a full range of accessible exercises

Editorial Reviews

Patterson and Hennessy's Computer Organization and Design has long been recognized as an exceptionally thorough and reliable introduction to computer design. Now they've fully updated their classic and linked it even more systematically to real-world practice.

You'll now find "Real Stuff" sections in every chapter: from Google clusters to advanced pipelining, AMD's Opteron memory hierarchy to recent innovations in Intel's Pentium line. You'll find new hardware coverage: FPGAs, HDL simulators, logic design conventions, and more. Plenty of new software coverage, too, from optimizing compilers to implementing object-oriented languages.

The meat of the book remains as good as ever: detailed, accessible introductions to modern instruction sets, memory, storage, networking, multiprocessing, clustering, and more. How it all fits. Why it works as it does. Whether you're primarily interested in hardware or software, this is the rock-solid grounding you'll need to succeed. Bill Camarda, from the October 2007 Read Only

The Barnes & Noble Review
Even today, to write great software, it helps to understand the underlying hardware. And if you’re a hardware architect, you’d better understand how your choices will impact developers. Computer Organization and Design, Third Edition will help software and hardware folks understand each other. The authors even provide separate learning paths for each audience.

Using the actual MIPS 32 architecture to ground their discussions in reality, David Patterson and John Hennessy illuminate computer arithmetic, pipelining, memory hierarchies, I/O, multiprocessing, clustering, and much more. Throughout, welcome “Fallacies and Pitfalls” sections clear up much of the misinformation that bedevils the field.

This edition’s been heavily updated, both for clarity and content. Especially worth noting: a stronger focus on the relationship between hardware and program performance, and a comparison of the Pentium 4 with AMD’s influential new Opteron. Bill Camarda

Bill Camarda is a consultant, writer, and web/multimedia content developer. His 15 books include Special Edition Using Word 2003 and Upgrading & Fixing Networks for Dummies, Second Edition.

bn.com

"...the fundamental computer organization book, both as an introduction for readers with no experience in computer architecture topics, and as an up-to-date reference for computer architects."—Computing Reviews, July 22 2014

From the Publisher