A Designer's Guide to Asynchronous VLSI

by Peter A. Beerel, Recep O. Ozdag, Marcos Ferretti

Overview

Create low power, higher performance circuits with shorter design times using this practical guide to asynchronous design. This practical alternative to conventional synchronous design enables performance close to full-custom designs with design times that approach commercially available ASIC standard cell flows. It includes design trade-offs, specific design examples, and end-of-chapter exercises. Emphasis throughout is placed on practical techniques and real-world applications, making this ideal for circuit design students interested in alternative design styles and system-on-chip circuits, as well as circuit designers in industry who need new solutions to old problems.

Product Details

ISBN-13:	9780511739163
Publisher:	Cambridge University Press
Publication date:	02/04/2010
Sold by:	Barnes & Noble
Format:	eBook
File size:	8 MB

About the Author

Peter A. Beerel is CEO of TimeLess Design Automation – his own company commercializing asynchronous VLSI tools and libraries – and an Associate Professor in the Electrical Engineering Department at the University of Southern California (USC). Dr Beerel has 15 years experience of research and teaching in asynchronous VLSI and has received numerous awards including the VSoE Outstanding Teaching Award in 1997 and the 2008 IEEE Region 6 Outstanding Engineer Award for significantly advancing the application of asynchronous circuits to modern VLSI chips.
Recep O. Ozdag is IC Design Manager at Fulcrum Microsystems and a part-time Lecturer at USC, where he received his Ph.D. in 2004. He is a recipient of the British Chevening Scholarship, the Turkish Ministry of Education Post-Graduate Scholarship and the Turkish Higher Education Council Scholarship.
Marcos Ferretti is one of the founders of PST Eletronica S. A. (Positron), Brazil - an automotive electronic systems manufacturing company, where he is currently Vice President of Technology. He received his Ph.D. from the University of Southern California (USC) in 2004 and was co-recipient of the USC Electrical Engineering-Systems Best Paper Award in the same year.

Table of Contents

1. Introduction; 2. Channel-based asynchronous design; 3. Modeling channel-based designs; 4. Pipeline performance; 5. Performance analysis and optimization; 6. Deadlock; 7. A taxonomy of design styles; 8. Synthesis-based controller design; 9. Micropipeline design; 10. Syntax-directed translation; 11. QDI pipeline templates; 12. Timed pipeline templates; 13. Single-track pipeline templates; 14. Asynchronous crossbar.