The Designer's Guide to VHDL / Edition 3

The Designer's Guide to VHDL / Edition 3

3.6 5
by Peter J. Ashenden
     
 

VHDL, the IEEE standard hardware description language for describing digital electronic systems, has recently been revised. This book has become a standard in the industry for learning the features of VHDL and using it to verify hardware designs. This third edition is the first comprehensive book on the market to address the new features of VHDL-2008.

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Overview

VHDL, the IEEE standard hardware description language for describing digital electronic systems, has recently been revised. This book has become a standard in the industry for learning the features of VHDL and using it to verify hardware designs. This third edition is the first comprehensive book on the market to address the new features of VHDL-2008.

* First comprehensive book on VHDL to incorporate all new features of VHDL-2008, the latest release of the VHDL standard...helps readers get up to speed quickly with new features of the new standard.
* Presents a structured guide to the modeling facilities offered by VHDL...shows how VHDL functions to help design digital systems.
* Includes extensive case studies and source code used to develop testbenches and case study examples..helps readers gain maximum facility with VHDL for design of digital systems.

Product Details

ISBN-13:
9780120887859
Publisher:
Elsevier Science
Publication date:
05/29/2008
Series:
Systems on Silicon Series, #3
Edition description:
New Edition
Pages:
936
Sales rank:
1,023,829
Product dimensions:
7.80(w) x 9.20(h) x 2.10(d)

Table of Contents

1 Fundamental Concepts
2 Scalar Data Types and Operations
3 Sequential Statements
4 Composite Data Types and Operations
5 Basic Modeling Constructs
6 Case Study: A Pipelined Complex Multiplier Accumulator
7 Subprograms
8 Packages and Use Clauses
9 Aliases
10 External Names in Testbenches
11 Properties and Assertion-Based Design
12 Resolved Signals
13 Generics
14 Components and Configurations
15 Generate Statements
16 Access Types and Abstract Data Types
17 Files and Input/Output
18 Case Study: Queuing Networks
19 Attributes and Groups
20 Design for Synthesis
21 Case Study: System Design using the Gumnut Core
22 Miscellaneous Topics
A Standard Packages
B Related Standards
C VHDL Syntax
D Differences Among VHDL Versions
E Answers to Exercises
References
Index

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