Designing CMOS Circuits for Low Power / Edition 1

Designing CMOS Circuits for Low Power / Edition 1

by Dimitrios Soudris, Christian Piguet, Costas Goutis
     
 

The fourth volume in a series on novel low-power design architectures, methods, and design practices to address the power needs of portable information and communication terminals in which a small battery has to last for long periods. Mostly Greek, but also other European scientists and engineers describe such methods as optimizing logical- level power, circuit… See more details below

Overview

The fourth volume in a series on novel low-power design architectures, methods, and design practices to address the power needs of portable information and communication terminals in which a small battery has to last for long periods. Mostly Greek, but also other European scientists and engineers describe such methods as optimizing logical- level power, circuit techniques for reducing power consumption in adders and multipliers, computer arithmetic techniques for low-power systems, and reducing power consumption in memories. They also cite case studies on safety-critical applications, and a low-power ultrasound beamformer ASIC. Annotation ©2003 Book News, Inc., Portland, OR

Product Details

ISBN-13:
9781402072345
Publisher:
Springer US
Publication date:
10/31/2002
Edition description:
2002
Pages:
290
Product dimensions:
6.14(w) x 9.21(h) x 0.81(d)

Meet the Author

Table of Contents

List of Figures. List of Tables. Contributing Authors. Foreword. Introduction. Part I: Low Power Design Methods. 1. Motivation, Context and Objectives; D. Soudris, C. Piguet, C. Goutis. 2. Sources of power dissipation in CMOS circuits; D. Soudris, A. Thanailakis. 3. Logic Level Power Optimization; G. Theodoridis, D. Soudris. 4. Circuit-Level Low-Power Design; S. Nikolaidis, A. Chatzigeorgiou. 5. Circuit Techniques for Reducing Power Consumption in Adders and Multipliers; L. Bisdounis, D. Gouvetas, O. Koufopavlou. 6. Computer Arithmetic Techniques for Low-Power Systems; V. Paliouras, T. Stouraitis. 7. Reducing Power Consumption in Memories; A. Chatzigeorgiou, S. Nikolaidis. 8. Low-Power Clock, Interconnect and Layout Designs; C. Piguet. 9. Logic Level Power Estimation; G. Theodoridis, C. Goutis. Part II: Low Power Design Stories. 10. Low-Power Design for Safety-Critical Applications; A. Kakarountas, K. Papadomanolakis, C. Goutis. 11. Design of a Low Power Ultrasound Beamformer ASIC; R. Schwann, T. Heselhaus, O. Weiss, T.G. Noll. 12. Epilogue; C. Piguet. Index.

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