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Designing CMOS Circuits for Low Power provides the fundamentals of low power design for logic, circuit, and physical design level as well as the "design story" of two innovative low power systems developed in the context of European Low Power Initiative for Electronic System Design. The main objective is to present in-depth analytical and design capabilities for low power design CMOS circuits.
List of Figures. List of Tables. Contributing Authors. Foreword. Introduction. Part I: Low Power Design Methods. 1. Motivation, Context and Objectives; D. Soudris, C. Piguet, C. Goutis. 2. Sources of power dissipation in CMOS circuits; D. Soudris, A. Thanailakis. 3. Logic Level Power Optimization; G. Theodoridis, D. Soudris. 4. Circuit-Level Low-Power Design; S. Nikolaidis, A. Chatzigeorgiou. 5. Circuit Techniques for Reducing Power Consumption in Adders and Multipliers; L. Bisdounis, D. Gouvetas, O. Koufopavlou. 6. Computer Arithmetic Techniques for Low-Power Systems; V. Paliouras, T. Stouraitis. 7. Reducing Power Consumption in Memories; A. Chatzigeorgiou, S. Nikolaidis. 8. Low-Power Clock, Interconnect and Layout Designs; C. Piguet. 9. Logic Level Power Estimation; G. Theodoridis, C. Goutis. Part II: Low Power Design Stories. 10. Low-Power Design for Safety-Critical Applications; A. Kakarountas, K. Papadomanolakis, C. Goutis. 11. Design of a Low Power Ultrasound Beamformer ASIC; R. Schwann, T. Heselhaus, O. Weiss, T.G. Noll. 12. Epilogue; C. Piguet. Index.