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Overview

Provides the only up-to-date source on the most recent advances in this often complex and fascinating topic.

  • The only book to be entirely devoted to clocking
  • Clocking has become one of the most important topics in the field of digital system design
  • A "must have" book for advanced circuit engineers
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Product Details

  • ISBN-13: 9780471274476
  • Publisher: Wiley
  • Publication date: 1/24/2003
  • Edition number: 1
  • Pages: 264
  • Product dimensions: 6.38 (w) x 9.37 (h) x 0.69 (d)

Meet the Author

VOJIN G. OKLOBDZIJA received his PhD from the University of California, Los Angeles. He has been a consultant for major computer and electronics companies in the fields of high-performance systems, low-power design, and fast data-path implementations with the emphasis on multi-media applications and has published extensively on the subjects of system design and computer engineering. Dr. Oklobdzija has worked at the IBM T.J. Watson Research Center where he did pioneering work on RISC architecture and machine development starting with the IBM 801. Currently, he is a professor in the Department of Electrical and Computer Engineering at the University of California, Davis, where he directs the Advanced Computer Systems Engineering Laboratory (ACSEL).

VLADIMIR M. STOJANOVIC is currently pursuing his PhD degree as a member of the VLSI research group, Electrical Engineering Department, Stanford University. He obtained MSEE degree from Stanford University and Dipl Ing diploma from Faculty of Electrical Engineering, University of Belgrade, Serbia. He was a research scholar at ACSEL.

DEJAN M. MARKOVIC received an Dipl Ing degree in Electrical Engineering from the University of Belgrade, Yugoslavia, in 1998 and an MS in Electrical Engineering from the University of California at Berkeley in 2000, where he is currently working toward a PhD. Mr. Markovic received the 2000-2001 CalVIEW Fellow Award for excellence in teaching and mentoring of industry engineers through the UC Berkeley distant learning program. He is a current member of the UC Berkeley Hitachi Fellow Team, conducting market research on Hitachi's Mu-Chip RFID technology.

NIKOLA NEDOVIC is currently pursuing his PhD in the Department of Electrical and Computer Engineering at the University of California, Davis. He was a research scholar at ACSEL, and has been published in seven papers.

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Read an Excerpt

Digital System Clocking

High-Performance and Low-Power Aspects
By Vojin G. Oklobdzija Vladimir M. Stojanovic Dejan M. Markovic Nikola M. Nedovic

John Wiley & Sons

ISBN: 0-471-27447-X


Chapter One

INTRODUCTION

Clocking is one of the single most important decisions facing the designer of a digital system. Unfortunately much too often it has been taken lightly at the beginning of a design and that viewpoint has proven to be very costly in the long run (Wagner 1988). Thus, it is not pretentious to dedicate an entire book to this subject. However, this book is limited to the even narrower issue of clocked storage elements (CSE), widely known as flip-flops and latches. The issues dealing with clock generation, frequency stability and control, and clock distribution are too numerous to be discussed in depth in this book and so they are covered only briefly. The interested reader is referred to the other books dealing with those issues, such as the one by Friedman (1995).

The importance of clocking has become even more emphasized, as the clock speed is rising rapidly, doubling every three years, as seen in Fig. 1.1. However, the clock uncertainties have not been scaling proportionally with the frequency increase, and an increasingly large portion of the clock cycle has been spent on the clocking overhead. The ability to absorb clock skew or to make the clocked storage element faster is reflected directly in the enhanced performance, since the performance is directly proportional to the clock frequency of a given system. Such performance improvements are very difficult to obtain using traditional techniques on the architecture or microarchitecture levels. The difficulties are caused by the overhead imposed by the CSE delay, and the clock uncertainties. Thus, setting the clock to the right frequency, and utilizing every available pico-second of the critical path, is increasingly important. It is our opinion that traditional clocking techniques will reach their limit when the clock frequency reaches the 5 to 10 GHz range. Thus, new ideas and new ways of designing digital systems are needed. We do not pretend to know what the future trend in clocking should be, but we feel that some of the ideas discussed in this book can provide a good path to follow.

Computers built in the past were large and filled several electronic cabinets in large air-conditioned rooms that occupied entire floors. They were built from discrete components or used a few large-scale integration (LSI) chips in the later models. Those systems were clocked at frequencies of about one or a few tens of megahertz, as shown in Table 1.1. The first electronic computer, ENIAC (Electronic Numerical Integrator and Calculator), for example, operated at the maximal clock frequency of 18 kHz. Given the low scale of integration, it was possible to "tune" the clock. This was achieved by either adjusting the length of the wires that distributed the clock signals, or by tuning the various delay elements on the cabinets or the circuit boards, so that the clock signal arrived at every circuit board at approximately the same time. With the advent of very large-scale integration (VLSI) technology, and increased integration levels, the ability to tune the clock has been greatly diminished. The clock signals are generated and distributed internally within the VLSI chip. Therefore, much of the burden of absorbing clock signal variations at various points on the VLSI chip has fallen on the clocked storage element.

1.1. CLOCKING IN SYNCHRONOUS SYSTEMS

The notion of clock and clocking is essential for the concept of synchronous design of digital systems. The synchronous system assumes the presence of the storage elements and combinational logic, which together make up a finite-state machine (FSM). The changes in the FSM are in general the result of two events: clock and input signal changes, as illustrated in Fig. 1.2.

The next state, [S.sub.n+1] is a function of the present state, [S.sub.n], and the logic value of the input signals: [S.sub.n+1] = [S.sub.n+1]([S.sub.n], [X.sub.n]). The remaining question is: When in time will FSM change to the next state, [S.sub.n+1]. This change is determined by the type of clocked storage elements used and the clock signal. The function of the clock signal is to provide a reference point in time when the FSM changes from the present, [S.sub.n], to the next state, [S.sub.n+1]. This process is illustrated in Fig. 1.3.

In Fig. 1.3, we have implicitly assumed that the moment when the state changes from [S.sub.n] to [S.sub.n+1] is determined by the change in the clock signal from logic "0" to logic "1." In fact, this change is determined by the type of clocked storage element and its functionality. We will be discussing this point in detail later in this book. For the purposes of this discussion, we observe that without the clock signal, the change from [S.sub.n] to [S.sub.n+1] could not be precisely determined. There are digital systems where this change is not caused by the presence, or more precisely, by a change in the clock signal, but by a change of the data signal, for example. Such systems are known as asynchronous systems, because they do not require the presence of the clock signal in order to effect an orderly transition from [S.sub.n] to [S.sub.n+1]. A great deal of research in defining a workable asynchronous system has been done in the last several decades. Recently a microprocessor was designed to operate in an asynchronous manner, and it has been claimed that some small advantages in power consumption were obtained (Woods et al. 1997). In spite of that, the practicality and advantage of the asynchronous design has yet to be proven (Furber et al. 2001). In this book, we limit our discussion to synchronous systems.

If we extend the FSM state diagram in time, we obtain an illustration of the pipeline design (Fig. 1.3). In many cases, when dealing with the synchronous design, the delay throughout the logic block is excessive and the signal change cannot propagate to the inputs of the clocked storage elements in time to effect the change to the next state. In that case, the machine has not met the "critical-path requirement." Such an FSM will fail in its functionality, because the changes initiated by the input signals will have no effect. This is because the time allowed to change to the next state, [S.sub.n+1]. is too short and the input signal change does not have sufficient time to propagate. In technical jargon this is known as critical-path violation. Critical path is defined as the chain of gates in the longest (slowest) path through the logic, which causes a signal to take a certain length of time to propagate from the input to the output. Often times, an additional state (or states) is inserted to assure that every transition proceeds in an orderly and timely fashion. This is known as pipelining. A diagram of a pipelined system is shown in Fig. 1.4.

Several clock cycles may be needed in order for the signal to propagate through various stages of a computer system. In general, execution of an instruction may require several machine cycles, where machine cycle is defined as the time interval necessary for one atomic operation to execute an instruction. One machine cycle normally takes several clock cycles. The machine cycle is often designated by a waveform defining its own cycle. This is especially true if microcode is used to control the machine. In the past, microcoding was a popular concept and it was used extensively in Complex Instruction Set Computers (CISC). In those cases, a process of executing an instruction required several machine cycles. During each machine cycle one microinstruction was executed. It normally took several microinstructions to execute an instruction. Each machine cycle required one or several register transfers or passes through several pipeline stages. That in turn required one or more clock cycles, or multiple phases of the clock. Thus, the clocking was quite complex and encompassed several levels of hierarchy. This is illustrated in Fig. 1.5, where three distinct machine cycles, Instruction Fetch, Dependency Resolution, and Instruction Issue, are shown. Dependency resolution can be quite a complex operation, requiring several register transfers, which means several clock cycles are necessary to complete this operation (as shown in Fig. 1.5). The machine would normally scan the cache block for several instructions and try to resolve any data dependencies. At the end of this cycle, operands will be fetched and placed in the corresponding registers (reservation stations) of the execution units.

In microcoded machines a large disparity existed between the speed of the clock and the speed of logic. It could take several clock cycles or even several tens or hundreds of clock cycles to execute one instruction. A more complex instruction required many more clock cycles. There could be tens of logic levels in the critical path, and 40 to 50 were not uncommon. Thus, the time associated with the clock and clocking was not as critical as it is today.

As the level of integration increased, combined with the increased speed of today's machines, the number of logic levels in the critical path started to diminish rapidly. Today's high-speed processors are either implementing Reduced Instruction Set Computer (RISC) architecture, or are running CISC code. However, to be able to efficiently implement superscalar execution cores, even CISC computers are translating their instructions into simple RISC-type operations called ROPs (RISC operations). Their microarchitecture can execute one or several ROPs in place of one CISC instruction. Therefore, the concept of microcoding has disappeared, as did the concept of machine cycle when implementing a particular machine architecture. The instructions (or ROPs) are executed in one cycle, which is usually driven by a single-phase clock. In other words, one instruction (or one ROP) is executed in every clock cycle. The levels of hierarchy that existed between the clock cycle and instruction execution no longer exist. In addition, the number and depth of pipeline stages keeps increasing in order to accommodate the trend toward increasing speed. As a result, the number of logic stages between the two CSEs keeps decreasing. Today 10 levels of logic in the critical path are more common. This number is still decreasing, as illustrated in Fig. 1.6. Any overhead associated with the clock system and clocking mechanism directly and adversely affects machine performance and is therefore critically important.

With this introduction we should be able to understand the function of the clock signal before we proceed with other definitions. The function of the clock signal is comparable to the function of the metronome in music. Similarly, in the digital system the clock designates the exact moment when the state is changing, as well as when the next state is to be captured. Also, all of the logic operations have to finish before the tick of the clock, because their final values are being captured by that clock event. Therefore, the clock provides the time reference point, which determines the flow of the data in the digital system.

1.2. SYSTEM CLOCK DESIGN

The clock system is usually divided into two distinct categories: clock generation and clock distribution. However, this classification should be extended by adding CSEs as an additional category, because the nature of the clocked storage elements is intimately connected to the clock system generation and distribution, and it is the nature of clocked storage elements that dictates the requirements imposed on the clock system. This relationship is best illustrated by the choice of clocking scheme, as shown in Fig. 1.7. The clock system can consist of a single-phase, a two-phase, or a multiple-phase clock. Transfer of data between CSEs in the system is usually accomplished by using an active phase of the clock. Thus, the clock phase controls the transfer of the information among the CSEs in the system. To prevent data from moving further then desired (achieving nontransparency), the clock phases are separated in time. This is referred to as nonoverlapped clock phases. In high-performance systems various phases of the clock can be overlapped in order to increase total system performance.

In the older systems it was more common to use multiple-phase clocks (Siewiorek et al. 1982). Transparent latches or flip-flops triggered by short pulses were used as storage elements. As the frequency of the operation kept increasing, it became exceedingly difficult to control various phases of the clock and their relationship to each other.

The two-phase clock is a robust scheme and is compatible with the design for testability, a desired feature of a complex computer system. Such a scheme, which incorporates a test mode, has been used in generations of IBM mainframe computers as a part of level-sensitive scan design (LSSD) methodology (LSSD 1985). The two nonoverlapping phases of the clock assure a robust clocking system that can tolerate manufacturing and process-parameter changes.

Given the continuing search for more speed and increased level of integration, even the two phases of the clock became difficult to control on the VLSI chip. This led to the widespread adoption of the single-phase clock in use today. Although two-phase clocking is still used, it is a single-phase clock that is distributed throughout the system, allowing the two necessary phases to be generated locally. This technique achieves two goals: (1) necessary amplification of the clock signals and ability to drive a large row of storage elements (register, for example), and (2) generation of two clock phases and compatibility with scan methodology. A scheme used for local two-phase clock generation from a single-phase clock distributed on the chip is shown in Fig. 1.8. Such a scheme is also capable of supporting the test and debug mode. The two phases of the clock, [C.sub.1] and [C.sub.2], are generated from the global clock CLKG. Specialized circuitry was added to allow for edge shifting at the cycle boundary (Sigal et al. 1997). Enabling and disabling of the clock phases is used to switch from normal operation to the scan mode that is used for testing.

1.2.1. Global System Clock Generation

Clock generation begins on a system board, where the global system clock reference is generated from a "crystal" oscillator. This is a circuit that uses a piezoelectric quartz crystal or some other ceramic material as a mechanical representation of an electrical inductance-capacitance-resistance (LRC) series resonant circuit. Piezoelectric effect in a material occurs with the exchange of energy between the mechanical forces and applied electric field. In quartz crystal, the physical dimensions of the lattice can very precisely determine the oscillation frequency. One excellent property of such resonators is their extremely high Q-factor, typically 1000-10,000. By attaching a nonlinear element (such as an NFET) to the resonator, the series resistance of the resonator is canceled by the negative resistance of the nonlinear element and "lossless" oscillations are maintained. Due to the high-quality Q-factor, the variation of the resonant frequency of the oscillator is only a few parts per million (ppm). Two realizations of the clock oscillator are shown in Fig. 1.9a and 1.9b.

System clock is set to directly correspond to the speed of data busses on the system board, that is, from 66 MHz, 100 MHz, 133 MHz, 266 MHz, and higher, in PC boards, to a few hundred MHz in specialized systems. However, the onchip clocks operate at frequencies that are in the GHz range. Even if the on-board clock signal of the same frequency as the on-chip clock could be generated, it would be very hard to bring it on-chip because of large parasitic capacitances and inductances in the package and bond-wires/balls that connect to the die. For these reasons, the low-frequency system clock is first brought on-chip and then frequency multiplication is performed to achieve the desired on-chip clock rate.

The time difference between the external clock and the internal clock, called insertion delay (shown in Fig. 1.10), increases relative to the clock period with the increase in the clock frequency. Input data are synchronized with the external clock, but can be stored directly in the storage elements clocked by the internal clock. Any insertion delay between the external and internal clocks directly impacts the cycle time of the processor. The insertion delay is caused by the onchip clock-driver delay, with the inverter chain representing the equivalent of the clock-driver tree, and clocked storage elements representing the total clock load. Several nF of the clock load are routinely encountered in modern microprocessor designs (Young et al. 1992). The clock-driver tree requires five or more fan-out of 4 (FO4) delays, which easily accounts for over 50% of the processor cycle time. Moreover, due to process and environmental variations, the delay of the clock driver may vary, causing an unknown phase relationship of the external and internal clocks.

(Continues...)



Excerpted from Digital System Clocking by Vojin G. Oklobdzija Vladimir M. Stojanovic Dejan M. Markovic Nikola M. Nedovic Excerpted by permission.
All rights reserved. No part of this excerpt may be reproduced or reprinted without permission in writing from the publisher.
Excerpts are provided by Dial-A-Book Inc. solely for the personal use of visitors to this web site.

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Table of Contents

Preface.

Introduction.

Theory of Clocked Storage Elements.

Timing and Energy Parameters.

Pipelining and Timing Analysis.

High-Performance System Issues.

Low-Energy System Issues.

Simulation Techniques.

State-of-the-Art Clocked Storage Elements in CMOS Technology.

Microprocesor Examples.

References.

Index.

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