Domain-Specific Processors: Systems, Architectures, Modeling and Simulation(Signal Processing and Communications Series)

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Assessment runs from realizations of the extended linearization model to optimization for piecewise regular processor arrays. Emphasizes efficiency in discussions of scalable parallel-pipelined and compiled regular architectures. Also covers single chip multiprocessing for consumer electronics.

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Product Details

  • ISBN-13: 9780824747114
  • Publisher: Taylor & Francis
  • Publication date: 11/11/2003
  • Series: Signal Processing and Communications Series
  • Edition description: New Edition
  • Pages: 280
  • Product dimensions: 6.25 (w) x 9.25 (h) x 1.25 (d)

Table of Contents

Automatic VHDL Model Generation of Parameterized FIR Filters, E.George Walters III, John Glossner, Michael J. Schulte; An LUT-Based High Level Synthesis Framework for Reconfigurable Architectures Lo c Lagadec, Bernard Pottier, and Oscar Villellas-Guillen; Highly Efficient Scalable Parallel-Pipelined Architectures for Discrete Wavelet Transforms David Guevorkian, Petri Liuha, Aki Launiainen and Ville Lappalainen; Stride Permutation Access in Interleaved Memory Systems, Jarmo Takala and Tuomas Jarvinen; Modelling of Intra-task Parallelism in Task-level Parallel Embedded Systems, Andy D. Pimentel, Frank P. Terpstra, Simon Polstra and Joe E. Coffland; Energy Estimation and Optimization for Piecewise Regular Processor Arrays, Frank Hannig and, Juergen Teich; Automatic Synthesis of Efficient Interfaces for Compiled Regular Architectures, Steven Derrien, Anne-Claire Quillou, Patrice Quinton, Tanguy Risset and Charles Wagner; Goal-Driven Reconfiguration of Polymorphous Architectures, Sumit Lohani and Shuvra S. Bhattacharyya; Realizations of the Extended Linearization Model, Alexandru Turjan, Bart Kienhuis, Ed Deprettere; Communication Services for Networks on Chip, Andrei Radulescu and Kees Goossens; Single chip Multiprocessing for Consumer Electronics, Paul Stravers and Jan Hoogerbugge; Future Directions of (Programmable and Reconfigurable) Embedded Processors, Stephan Wong, Stamatis Vassiliadis, Sorin Cotofana.

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