Electronic Design Automation: Synthesis, Verification, and Test

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This book provides broad and comprehensive coverage of the entire EDA flow. EDA/VLSI practitioners and researchers in need of fluency in an "adjacent" field will find this an invaluable reference to the basic EDA concepts, principles, data structures, algorithms, and architectures for the design, verification, and test of VLSI circuits. Anyone who needs to learn the concepts, principles, data structures, algorithms, and architectures of the EDA flow will benefit from this book.

  • Covers complete spectrum of the EDA flow, from ESL design modeling to logic/test synthesis, verification, physical design, and test - helps EDA newcomers to get "up-and-running" quickly
  • Includes comprehensive coverage of EDA concepts, principles, data structures, algorithms, and architectures - helps all readers improve their VLSI design competence
  • Contains latest advancements not yet available in other books, including Test compression, ESL design modeling, large-scale floorplanning, placement, routing, synthesis of clock and power/ground networks - helps readers to design/develop testable chips or products
  • Includes industry best-practices wherever appropriate in most chapters - helps readers avoid costly mistakes
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Product Details

  • ISBN-13: 9780123743640
  • Publisher: Elsevier Science
  • Publication date: 2/26/2009
  • Series: Systems on Silicon Series
  • Edition description: New Edition
  • Pages: 972
  • Product dimensions: 7.80 (w) x 9.40 (h) x 1.80 (d)

Meet the Author

Laung-Terng Wang, Ph.D., is founder, chairman, and chief executive officer of SynTest Technologies, CA. He received his EE Ph.D. degree from Stanford University. A Fellow of the IEEE, he holds 18 U.S. Patents and 12 European Patents, and has co-authored/co-edited two internationally used DFT textbooks- VLSI Test Principles and Architectures (2006) and System-on-Chip Test Architectures (2007).

Yao-Wen Chang, Ph.D., is a Professor in the Department of Electrical Engineering, National Taiwan University. He recevied his Ph.D. degree in Computer Science from the University of Texas at Austin. He has published over 200 technical papers, co-authored one book, and is a winner of the ACM ISPD Placement (2006) and Global Routing (2008) contests.

Kwang-Ting (Tim) Cheng, Ph.D., is a Professor and Chair of the Electrical and Computer Engineering Department at the University of California, Berkeley. A Fellow of the IEEE, he has published over 300 technical papers, co-authored three books, and holds 11 U.S. Patents.

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Read an Excerpt

Electronic Design Automation: Synthesis, Verification, and Test

Morgan Kaufmann Publishers

Copyright © 2009 Elsevier Inc.
All right reserved.

ISBN: 978-0-08-092200-3

Chapter One


Charles E. Stroud Auburn University, Auburn, Alabama

Laung-Terng (L.-T.) Wang SynTest Technologies, Inc., Sunnyvale, California

Yao-Wen Chang National Taiwan University, Taipei, Taiwan


Electronic design automation (EDA) is at the center of technology advances in improving human life and use every day. Given an electronic system modeled at the electronic system level (ESL), EDA automates the design and test processes of verifying the correctness of the ESL design against the specifications of the electronic system, taking the ESL design through various synthesis and verification steps, and finally testing the manufactured electronic system to ensure that it meets the specifications and quality requirements of the electronic system. The electronic system can also be a printed circuit board (PCB) or simply an integrated circuit (IC). The integrated circuit can be a system-on-chip (SOC), application-specific integrated circuit (ASIC), or a field programmable gate array (FPGA).

On one hand, EDA comprises a set of hardware and software co-design, synthesis, verification, and test tools that check the ESL design, translate the corrected ESL design to a register-transfer level (RTL), and then takes the RTL design through the synthesis and verification stages at the gate level and switch level to eventually produce a physical design described in graphics data system II (GDSII) format that is ready to signoff for fabrication and manufacturing test (commonly referred to as RTL to GDSII design flow). On the other hand, EDA can be viewed as a collection of design automation and test automation tools that automate the design and test tasks, respectively. The design automation tools deal with the correctness aspects of the electronic system across all levels, be it ESL, RTL, gate level, switch level, or physical level. The test automation tools manage the quality aspects of the electronic system, be it defect level, test cost, or ease of self-test and diagnosis.

This chapter gives a more detailed introduction to the various types and uses of EDA. We begin with an overview of EDA, including some historical perspectives, followed by a more detailed discussion of various aspects of logic design, synthesis, verification, and test. Next, we discuss the important and essential process of physical design automation. The intent is to orient the reader for the remaining chapters of this book, which cover related topics from ESL design modeling and synthesis (including high-level synthesis, logic synthesis, and physical synthesis) to verification and test.


EDA has had an extraordinary effect on everyday human life with the development of conveniences such as cell phones, global positioning systems (GPS), navigation systems, music players, and personal data assistants (PDAs). In fact, almost everything and every daily task have been influenced by, and in some cases are a direct result of, EDA. As engineers, perhaps the most noteworthy inventions have been the microprocessor and the personal computer (PC), their progression in terms of performance and features, and the subsequent development of smaller, portable implementations such as the notebook computer. As a result, the computer has become an essential tool and part of everyday life—to the extent that current automobiles, including safety features in particular, are controlled by multiple microprocessors. In this section, we give a brief overview of the history of EDA in its early years.

1.1.1 Historical perspective

The history of electronic design automation (EDA) began in the early 1960s after the introduction of integrated circuits (ICs) [Kilby 1958]. At this very early stage, logic design and physical design of these ICs were mainly created by hand in parallel. Logic design constructed out of wired circuit boards that mimic the physical design of the IC was built to simulate and verify whether the IC will function as intended before fabrication. The ACM and IEEE cosponsored the Design Automation Conference (DAC) debut in 1964 in a joint effort to automate and speed up the design process [DAC 2008]. However, it was not until the mid-1970s when mainframe computers and minicomputers were, respectively, introduced by IBM and Digital Equipment Corporation (DEC) that design automation became more feasible.

During this period, EDA research and development was typically internal to large corporations such as Bell Labs, Hewlett Packard, IBM, Intel, and Tektronix. The first critical milestones in EDA came in the form of programs for circuit simulation and layout verification. Various proprietary simulation languages and device models were proposed. The SPICE models were used in circuit simulation (commonly referred to as SPICE simulation now) to verify whether the then so-called logic design specified at the transistor level (called transistor-level design) will behave the same as the functional specifications. This removes the need to build wired circuit boards. At the same time, layout verification tools that took SPICE models as inputs were developed to check whether the physical design would meet layout design rules and then tape out the physical design in the graphics data system II (GDSII) format introduced by Calma in the mid-1970s.

Although circuit simulation and layout verification ensure that the logic design and physical design will function correctly as expected, they are merely verification tools; design automation tools are needed to speed up the design process. This requires logic simulation tools for logic design at the gate level (rather than at the transistor level) and place and route (P&R) tools that operate at the physical level to automatically generate the physical design. The Tegas logic simulator that uses the Tegas description language (TDL) was the first logic simulator that came to widespread use until the mid-1990s, when industry began adopting the two IEEE developed hardware description language (HDL) standards: Verilog [IEEE 1463-2001] and VHDL [IEEE 1076-2002]. The first graphical software to assist in the physical design of the IC in the late 1960s and early 1970s was introduced by companies like Calma and Applicon. The first automatic place and route tools were subsequently introduced in the mid-1970s. Proprietary schematic capture and waveform display software to assist in the logic design of the IC was also spurring the marketplace.

Although much of the early EDA research and development was done in corporations in the 1960s and 1970s, top universities including Stanford, the University of California at Berkeley, Carnegie Mellon, and California Institute of Technology had quietly established large computer-aided design (CAD) groups to conduct research spreading from process/device simulation and modeling [Dutton 1993; Plummer 2000] to logic synthesis [Brayton 1984; De Micheli 1994; Devadas 1994] and analog and mixed signal (AMS) design and synthesis [Ochetta 1994] to silicon compilation and physical design automation [Mead 1980]. This also marks the timeframe in which EDA began as an industry with companies like Daisy Systems, Mentor Graphics [Mentor 2008], and Valid Logic Systems (acquired by Cadence Design Systems [Cadence 2008]) in the early 1980s. Another major milestone for academic-based EDA research and development was the formation of the Metal Oxide Semiconductor Implementation Service (MOSIS) in the early 1980s [MOSIS 2008].

Since those early years, EDA has continued to not only provide support and new capabilities for electronic system design but also solve many problems faced in both design and testing of electronic systems. For example, how does one test an IC with more than one billion transistors to ensure with a high probability that all transistors are fault-free? Design for testability (DFT) and automatic test pattern generation (ATPG) tools have provided EDA solutions. Another example is illustrated in Figure 1.1 for mask making during deepsubmicron IC fabrication. In this example, the lithographic process is used to create rectangular patterns to form the various components of transistors and their interconnections. However, sub-wavelength components in lithography cause problems in that the intended shapes become irregular as shown in Figure 1.1. This problem posed a serious obstacle to advances in technology in terms of reducing feature size, also referred to as shrinking design rules, which in turn increases the number of transistors that can be incorporated in an IC. However, EDA has provided the solution through optical proximity correction (OPC) of the layout to compensate for rounding off feature corners.

1.1.2 VLSI design flow and typical EDA flow

When we think of current EDA features and capabilities, we generally think of synthesis of hardware description languages (HDLs) to standard cell–based ASICs or to the configuration data to be downloaded into FPGAs. As part of the synthesis process, EDA also encompasses design audits, technology mapping, and physical design (including floorplanning, placement, routing, and design rule checking) in the intended implementation medium, be that ASIC, FPGA, PCB, or any other media used to implement electronic systems. In addition, EDA comprises logic and timing simulation and timing analysis programs for design verification of both pre-synthesis and post-synthesis designs. Finally, there is also a wealth of EDA software targeting manufacturing test, including testability analysis, automatic test pattern generation (ATPG), fault simulation, design for testability (DFT), logic/memory built-in self-test (BIST), and test compression.

In general, EDA algorithms, techniques, and software can be partitioned into three distinct but broad categories that include logic design automation, verification and test, and physical design automation. Although logic and physical design automation are somewhat disjointed in that logic design automation is performed before physical design automation, the various components and aspects of the verification and test category are dispersed within both logic and physical design automation processes. Furthermore, verification software is usually the first EDA tool used in the overall design method for simulation of the initial design developed for the intended circuit or system.


Excerpted from Electronic Design Automation: Synthesis, Verification, and Test Copyright © 2009 by Elsevier Inc.. Excerpted by permission of Morgan Kaufmann Publishers. All rights reserved. No part of this excerpt may be reproduced or reprinted without permission in writing from the publisher.
Excerpts are provided by Dial-A-Book Inc. solely for the personal use of visitors to this web site.

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Table of Contents

Chapter 1: Introduction Chapter 2: Fundamentals of CMOS Design Chapter 3: Design for Testability Chapter 4: Fundamentals of Algorithms Chapter 5: Electronic System-Level Design and High-Level Synthesis Chapter 6: Logic Synthesis in a Nutshell Chapter 7: Test Synthesis Chapter 8: Logic and Circuit Simulation Chapter 9:Functional Verification Chapter 10: Floorplanning Chapter 11: Placement Chapter 12: Global and Detailed Routing Chapter 13: Synthesis of Clock and Power/Ground Networks Chapter 14: Fault Simulation and Test Generation.

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