ESD: Circuits and Devices / Edition 1

Hardcover (Print)
Used and New from Other Sellers
Used and New from Other Sellers
from $97.99
Usually ships in 1-2 business days
(Save 40%)
Other sellers (Hardcover)
  • All (5) from $97.99   
  • New (4) from $97.99   
  • Used (1) from $130.45   

Overview

The scaling of semiconductor devices from sub-micron to nanometer dimensions is driving the need for understanding the design of electrostatic discharge (ESD) circuits, and the response of these integrated circuits (IC) to ESD phenomena.

ESD Circuits and Devices provides a clear insight into the layout and design of circuitry for protection against electrical overstress (EOS) and ESD.  With an emphasis on examples, this text:

  • explains ESD buffering, ballasting, current distribution, design segmentation, feedback, coupling, and de-coupling ESD design methods;
  • outlines the fundamental analytical models and experimental results for the ESD design of MOSFETs and diode semiconductor device elements, with a focus on CMOS, silicon on insulator (SOI), and Silicon Germanium (SiGe) technology;
  • focuses on the ESD design, optimization, integration and synthesis of these elements and concepts into ESD networks, as well as applying within the off-chip driver networks, and on-chip receivers; and
  • highlights state-of-the-art ESD input circuits, as well as ESD power clamps networks.

Continuing the author’s series of books on ESD, this book will be an invaluable reference for the professional semiconductor chip and system ESD engineer.  Semiconductor device and process development, quality, reliability and failure analysis engineers will also find it an essential tool.  In addition, both senior undergraduate and graduate students in microelectronics and IC design will find its numerous examples useful.

Read More Show Less

Product Details

  • ISBN-13: 9780470847541
  • Publisher: Wiley
  • Publication date: 1/6/2006
  • Edition number: 1
  • Pages: 412
  • Sales rank: 896,458
  • Product dimensions: 6.97 (w) x 9.94 (h) x 1.11 (d)

Meet the Author

Dr. Steven H. Voldman received his B. S. in Engineering Science from the University of Buffalo (1979); M.S. EE (1981) and Electrical Engineer Degree (1982) from M.I.T.; MS Engineering Physics (1986) and Ph.D. EE (1991) from the University of Vermont under IBM Resident Study Fellow program. At M.I.T., he worked as a member of the M.I.T. Plasma Fusion center, and the High Voltage Research Laboratory (HVRL). At IBM, as a reliability/device engineer, his work included pioneering work in bipolar/CMOS SRAM alpha particle and cosmic ray SER simulation, MOSFET gate-induced drain leakage (GIDL) mechanism, hot electron, epitaxy/well design, CMOS latchup, and ESD. Since 1986, he was responsible for defining the IBM ESD/latchup strategy for CMOS, SOI, BiCMOS and RF CMOS, and SiGe technologies. He has authored ESD and latchup publications in the area of MOSFET scaling, device simulation, copper, low-k, MR heads, CMOS, SOI, SiGe and SiGeC technology. Voldman served as SEMATECH ESD Working Group Chairman (1996–2000), ESD Association Technical Program Chair (2000), Vice Chairman (2001), General Chairman 2002, and ESDA Board of Directors (1998–2006), International Reliability Physics Symposium ESD/Latchup Sub-Committee Chairman (2002–2006), International Physical and Failure Analysis (IPFA) Symposium ESD Sub-Committee Chairman (2003–2005), ESD Association Standard Development Chairman on Transmission Line Pulse Testing (2000–2006), ESD International Committee on Education (ICE) Asian University Liason and “ESD on Campus” program founder, and serves in the ISQED Committee, Taiwan ESD Conference (T-ESDC) Technical Program Committee (Hsinchu, Taiwan), and the International Conference on Electromagnetic Compability (ICEMAC, Taipei, Taiwan). Voldman has provided ESD lectures for universities (e.g., M.I.T. Lecture Series, Taiwan National Chiao-Tung University (NCTU), and Singapore Nanyang Technical University (NTU)). He is a recipient of over 136 U.S. patents, over 100 publications, and recently wrote a textbook on ESD entitled ESD: Physics and Devices (John Wiley and Sons, Ltd) as well as contributing to the text “Silicon Germanium: Modeling, Technology and Simulation,” and providing talks on patenting and invention. He has been highlighted in EE Times, Intellectual Property Law and Business and authored the first article on ESD phenomena for the October 2002 edition of Scientific American entitled “Lightning Rods for Nano-electronics,” and Pour La Science, Le Scienze, and Swiat Nauk International editions. In 2003, Dr. Voldman was accepted as the first IEEE Fellow for ESD phenomena in semiconductors for “contributions to electrostatic discharge protection in CMOS, SOI, and SiGe technologies.”

Read More Show Less

Read an Excerpt

ESD

Circuits and Devices
By Steven Howard Voldman

John Wiley & Sons

Copyright © 2006 John Wiley & Sons. Ltd.
All right reserved.

ISBN: 0-470-84754-9


Chapter One

Electrostatic Discharge

1.1 ELECTRICITY AND ELECTROSTATICS DISCHARGE

1.1.1 Electricity and Electrostatics

In the field of electricity, electrostatics, and circuit theory, there are many discoveries and accomplishments that have lead to the foundation of the field of electrostatic discharge (ESD) phenomenon. Below is a chronological list of key events that moved the field of electrostatics forward:

600 B.C. Thales of Miletus discovers electrostatic attraction.

1600 A.D. William Gilbert proposes the "electric fluid" model.

1620 A.D. Niccolo Cabeo discusses "attractive" and "repulsive" phenomena.

1729 A.D. Stephen Gray demonstrates "electricity" can be transferred by wires.

1733 A.D. Charles Francois du Fay discusses two kinds of electricity-"resinous" and "vitreous."

1749 A.D. Abbey Jean-Antoine Nollet invents the two-fluid model of electricity.

1745 A.D. Pieter Van Musschenbroeck invents the Leyden jar, or the capacitor.

1747 A.D. Benjamin Franklin proposes single fluid model, with "positive" and "negative" charge.

1748 A.D. Sir William Watson develops the first "glow discharge."

1759 A.D. Francis Ulrich Theodore Aepinus discusses "charging by induction."

1766 A.D. Joseph Priestley deduces the electric force follows an inverse square law.

1775 A.D. Henry Cavendish invents the concept of capacitance and resistance.

1785 A.D. Charles Augustin Coulomb verifies the inverse square law relationship.

1812 A.D. Simeon Denis Poisson demonstrates that charge resides on the surface of a conductor.

1821 A.D. Humphrey Davy establishes the geometrical and thermal effects of resistance.

1826 A.D. Ohm develops the relationship between potential, resistance, and current.

1837 A.D. Michael Faraday discovers the concept of dielectric constants in materials.

1841 A.D. James Prescott Joule shows relationship of electrical current and thermal heating.

1848 A.D. Gustav Kirchoff extends the concept of Ohm's law.

1873 A.D. James Clerk Maxwell publishes the work Treatise of Electricity and Magnetism.

1889 A.D. Paschen establishes a relationship explaining the electrical breakdown of gases.

1906 A.D. Toepler establishes a relationship for arc resistance in a discharge process.

1915 A.D. Townsend explains avalanche phenomena in materials.

1.1.2 Electrostatic Discharge

In the field of ESD, accomplishments to advance the field of electrostatic discharge phenomena are in the form of development of experimental discovery, analytical models, introduction of new semiconductor devices and circuits, test equipment, as well as the development of ESD standards. Below is a short chronological list of key events that moved the field of ESD:

1968 A.D. D. Wunsch and R. R. Bell introduces the power-to-failure electro-thermal model in the thermal diffusion time constant regime.

1970 A.D. D. Tasca develops the power-to-failure electro-thermal model in the adiabatic and steady-state time constant regime.

1971 A.D. Vlasov and Sinkevitch develops a physical model for electro-thermal failure of semiconductor devices.

1972 A.D. W. D. Brown evaluates semiconductor devices under high-amplitude current conditions.

1981 A.D. J. Smith and W. R. Littau develops an electro-thermal model for resistors in the thermal diffusion time regime.

1981 A.D. Enlow, Alexander, Pierce, and Mason addresses the statistical variation of the power-to-failure of bipolar transistors due to semiconductor manufacturing process, and ESD event variations.

1983 A.D. M. Ash evaluates the non-linear nature of the power threshold and the temperature dependence of the physical parameters establishing the Ash relationship.

1983 A.D. V. I. Arkihpov, E. R. Astvatsaturyan, V. I. Godovosyn, and A. I. Rudenko derives the cylindrical nature of the electro-current constriction.

1985 A.D. T. J. Maloney and N. Khurana discusses transmission line pulse (TLP) testing as a method for semiconductor I-V characterization and modeling.

1989 A.D. Dwyer, Franklin, and Campbell extends the Wunsch-Bell model to address three-dimensional effects.

1989 A.D. R. Renninger, M. Jon, D. Lin, T. Diep, and T. Welser introduces the first field-induced charged device model (CDM) device simulator.

1989 A.D. T. Polgreen and P. Chatterjee explain non-uniform current flow in silicided multi-finger MOSFETs.

1992 A.D. M. Hargrove and S. Voldman quantify CMOS ESD networks in the first CMOS shallow trench isolation (STI) technology.

1992 A.D. S. Voldman discovers the effect of MeV implanted retrograde well dose on ESD robustness.

1993 A.D. D. Lin publishes the first paper on the effect of MOSFET dielectric and junction breakdown scaling on on-chip ESD protection.

1993 A.D. S. Voldman publishes the first paper on the influence on MOSFET constant electric field scaling theory on ESD robustness [16]. A "Constant ESD scaling" theory is developed under the constraint of maintaining ESD robustness as technology is scaled.

1993 A.D. ESD Association releases the human body model (HBM) standard for semiconductor component testing.

1993 A.D. H. Geiser introduces the very fast transmission line pulse (VF-TLP) ESD test system.

1994 A.D. A. Ameresekera and C. Duvvury publishes on the influence of MOSFET scaling trends on ESD robustness.

1994 A.D. ESD Association releases the machine model (MM) standard for semiconductor component testing.

1995 A.D. A. Wallash releases the first publication on ESD failure mechanisms in magneto-resistor (MR) recording heads. The significance of the work was the first indication of ESD concerns in the magnetic recording and disk drive industry.

1995 A.D. SEMATECH initiates ESD Working Group to address ESD strategic planning. The SEMATECH effort addresses ESD technology benchmarking, ESD technology roadmap and test equipment, ESDA and JEDEC ESD specification alignment, and TLP test standard development.

1996 A.D. K. Banerjee develops Ti/Al/Ti interconnect model, extending the work of D. Tasca to modern CMOS interconnects.

1997 A.D. S. Voldman publishes first experimental measurements of ESD in copper (Cu) interconnects, and the comparison to aluminum (Al) interconnects. This work addresses the influence of CMOS interconnect scaling on ESD robustness, and the evolutionary changes from aluminum to copper interconnects.

1997 A.D. ESD Association Device Testing Standards Committee releases first charged device model (CDM) Standard.

1997 A.D. J. Barth introduces the first commercial transmission line pulse (TLP) device simulator. The introduction of commercial systems has lead to the acceptance of the TLP methodology for ESD sensitivity testing of semiconductors.

1998 A.D. SEMATECH Quality and Reliability ESD Working Group initiates transmission line pulse (TLP) standards effort.

2000 A.D. S. Voldman and P. Juliano published the first ESD measurements in Silicon Germanium (SiGe) technology. The significance of this work is the beginning of the focus of ESD in radio frequency (RF) technology.

2002 A.D. R. Gibson and J. Kinnear initiate the S20.20 ESD Control Certification Program. The significance of this effort is the focus on international certification of ESD control programs.

2003 A.D. Oryx Instruments and Thermo KeyTek, introduces commercial very fast transmission line pulse (VF-TLP) systems. The significance of this work is the introduction of VF-TLP systems as a standard testing methodology for future ESD testing.

2004 A.D. ESD Association Device Testing Standards Committee initiates the transmission line pulse (TLP) Standard Practice document. The significance of this work is the acceptance of TLP as a standard testing methodology in the semiconductor industry.

1.1.3 Key ESD Patents, Inventions, and Innovations

In the field of ESD protection, there are many patents, inventions, and innovations that stimulated growth of ESD circuits as well as improved the ESD robustness of circuits themselves. ESD circuit inventions are important in providing innovations and techniques that improve the ESD robustness of semiconductor chips. Interest in ESD patenting of ESD protection networks began in the 1970s, with a continued growth in patent activity, invention, and innovations. Below is a chronological list of key innovations that moved the field of ESD protection forward in the area of ESD circuits. In some cases, no patent for the invention was pursued. Many of the patents chosen in this listing consist of the ESD design practices and subjects and topics which will be discussed in the text. Starting from the 1970s, here is a listing of key circuit innovations and those which will be referred to in the future chapters:

1970 A.D. M. Fischer (IBM). Resistor-thick oxide FET gate protection device for thin oxide FETs. IBM Technology Disclosure Bulletin 13 (5): 1272-1273. This introduced the use of a gate-coupled "thick oxide" field effect transistor and a series resistor element. This invention discloses the concept of using a thick oxide insulated gate field effect transistor (IGFET) to protect a thin oxide IGFET.

1971 A.D. Boss et al. (IBM). ESD network with capacitor divider and half-pass transmission gate. IBM Technology Disclosure Bulletin. This introduced the concept of using a capacitive divider across a half-pass transmission gate to reduce the gate oxide stress.

1971 A.D. M. Lenzlinger (RCA). ESD distributed diode/resistor double-diode network. RCA Corporation, CD 4013. Publication: "Gate Protection of MIS Devices", M. Lenzlinger, IEEE Transactions on Electron Device ED-18 (4): 1971. This publication discloses the concept of a double-diode ESD network as well as a distributed diode-resistor transmission line for the diode to [V.sub.DD].

1973 A.D. G. W. Steudel (RCA). Input transient protection for complimentary field effect transistor integrated circuit device. U.S. Patent No. 3,712,995, January 23, 1973. The patent shows a distributed double-diode ESD network with diode/resistor distributed network, but with the reverse polarity.

1974 A.D. T. Enomoto and H. Morita (Mitsubishi). Semiconductor device. U.S. Patent No. 3,819,952, June 25, 1974. The patent shows the use of a first-stage gate-coupled thick oxide insulated gate field effect transistor (IGFET), a series resistor element (prior to the IGFET drain), and a IGFET source resistor element. This first stage is followed by a second-stage thin oxide IGFET whose gate is coupled to the first-stage IGFET source node. The network introduces the concept of a first- and second-stage ESD network, gate-coupling, series resistor options, as well introduces a de-biasing resistor at the source of the first stage.

1979 A.D. C. Bertin (IBM). Over-voltage protective device and circuits for insulated gate transistors. U.S. Patent No. 4,139,935, February 20, 1979. This patent by Claude Bertin was the first process patent that produced a metallurgical junction with a lower breakdown voltage using junction "tailoring" where the breakdown element was to serve as a "gate tie down" or protection network for MOSFET gate oxides.

1983 A.D. N. Sasaki (Fujitsu). Semiconductor integrated circuit device providing a protection circuit. U.S. Patent No. 4,423,431. December 27, 1983. Sasaki introduces the idea of use of a series resistor, and thin oxide transistor as a protection network. The network also introduces gate-coupled thin oxide and a resistor in series with the capacitor. This is the first network that is using gate-coupled thin oxide devices with a resistor on the gate electrode to ground, in a single-stage implementation.

1983 A.D. L. Avery (RCA). Integrated circuit protection device. U.S. Patent No. 4,400,711. August 23, 1983. This patent used a MOSFET in the regenerative feedback loop of a pnpn silicon-controlled rectifier (SCR) for ESD protection applications.

1989 A.D. C. Duvvury and R. Rountree (Texas Instruments). Output buffer with improved ESD protection. U.S. Patent No. 4,855,620, August 8, 1989. This patent is the first patent to discuss the optimization of output buffers for ESD protection improvements.

1990 A.D. R. Rountree (Texas Instruments). Circuit structure with enhanced electrostatic discharge protection. U.S. Patent No. 4,939,616, July 3, 1990. This patent discusses the formation of a low-voltage trigger pnpn silicon-controlled rectifier (SCR) using an n+ diffusion that extends outside of the n-well region to form a lower breakdown voltage and lateral npn element. This innovation was important to produce low-voltage trigger SCRs as technology began to scale.

1992 A.D. A. Graham (Gazelle). Structure for providing electrostatic discharge protection. U.S. Patent No. 5,124,877, June 23, 1992. This patent introduces the concept of a diode string as well as a "ESD discharge reference rail." Today, ESD diode strings are commonly used, as well as the discharge rail concept.

1993 A.D. W. Miller (National Semiconductor). Electrostatic discharge detection and clamp control circuit. U.S. Patent No. 5,255,146, October 19, 1993. This patent was the first patent RC-triggered ESD power clamp network to address the presence of "detection circuits" which respond to the ESD pulse. This is the first patent that addresses the usage of an RC network which is chosen to be responsive to the ESD pulse network.

1993 A.D. R. Merrill (National Semiconductor). Electrostatic discharge protection for integrated circuits. U.S. Patent No. 5,239,440, August 24, 1993. This innovation utilized the RC-discriminator network, inverter logic, and logic circuitry that is parallel to the pre-drive circuitry, and turns on the I/O off-chip driver (OCD) output stage during ESD events.

1993 A.D. Kirsch, G. Gerosa, and S. Voldman (Motorola and IBM). Snubber-clamped ESD diode string network. This network introduced a diode string as a mixed-voltage interface network and solved the reverse-Darlington amplification using a "Snubber" diode element. Implemented into the PowerPC microprocessor and embedded controller family. This was applied to advanced microprocessors for mixed-voltage applications.

1994 A.D. D. Puar (Cirrus Logic). Shunt circuit for electrostatic discharge protection. U.S. Patent No. 5,287,241, February 15, 1994. This introduced the first RC-triggered p-channel MOSFET-based ESD power clamp network.

1994 A.D. J. Pianka (AT&T). ESD protection of output buffers. U.S. Patent No. 5,345,357, September 6, 1994. Development of RC-trigger and gate coupling circuit elements for activation of the output of an n-channel MOSFET pull-up and pull-down off-chip driver (OCD). This ESD technique is especially valuable for small computer system interface (SCSI) chips, since only n-channel output transistors are used as the pull-up and pull-down elements.

1996 A.D. T. J. Maloney (Intel). Electrostatic discharge protection circuits using biased and terminated PNP transistor chains. U.S. Patent No. 5,530,612, June 25, 1996. Maloney's patent application was a second ESD circuit application to address the leakage amplification in diode string ESD networks. This was applied to advanced microprocessors for mixed-voltage applications.

1997 A.D. S. Voldman, S. Geissler, and E. Nowak (IBM). Semiconductor diode with silicide films and trench isolation. U.S. Patent No. 5,629,544, May 13, 1997. This is the first patent that addresses four items: first, it addresses ESD diode structures constructed in shallow trench isolation; second, it addresses STI pull-down effects; it addresses the lateral polysilicon-bound gated ESD p-n diodes; and fourth, the silicon-on-insulator (SOI) lateral ESD gated diode structures.

1997 A.D. D. Krakauer, K. Mistry, S. Butler, and H. Partovi, (Digital Corp). Self-referencing modulation circuit for CMOS integrated circuit electrostatic discharge protection clamps. U.S. Patent No. 5,617,283, April 1, 1997. This was the first ESD application using MOSFETs to establish a MOSFET gate-modulation network. This was applied to microprocessor applications.

(Continues...)



Excerpted from ESD by Steven Howard Voldman Copyright © 2006 by John Wiley & Sons. Ltd.. Excerpted by permission.
All rights reserved. No part of this excerpt may be reproduced or reprinted without permission in writing from the publisher.
Excerpts are provided by Dial-A-Book Inc. solely for the personal use of visitors to this web site.

Read More Show Less

Table of Contents

About the Author.

Preface.

Acknowledgments.

Chapter 1: Electrostatic Discharge.

1.1 Electricity and Electrostatics Discharge.

1.2 Fundamental Concepts of ESD Design.

1.3 Time Constants.

1.4 Capacitance, Resistance and Inductance and ESD.

1.5 Rules of Thumb and ESD.

1.6 Lumped versus Distributed Analysis and ESD.

1.7 ESD Metrics and Figures of Merit.

1.8 Twelve Steps to Building an ESD Strategy.

1.9 Summary and Closing Comments.

Problems.

References.

Chapter 2: Design Synthesis.

2.1 Synthesis and Architecture of a Semiconductor Chip for ESD Protection.

2.2 Electrical and Spatial Connectivity.

2.3 ESD, Latchup, and Noise.

2.4 Interface Circuits and ESD Elements.

2.5 ESD Power Clamps Networks.

2.6 ESD Rail-to-Rail Devices.

2.7 Guard Rings.

2.8 Pads, Floating Pads, and No Connect Pads.

2.9 Structures Under Bond Pads.

2.10 Summary and Closing Comments.

Problems.

References.

Chapter 3: Electrostatic Discharge (ESD) Design: MOSFET Design.

3.1 Basic ESD Design Concepts.

3.2 ESD MOSFET Design: Channel Width.

3.3 ESD MOSFET Design: Contact.

3.4 ESD MOSFET Design: Metal Distribution.

3.5 ESD MOSFET Design: Silicide Masking.

3.6 ESD MOSFET Design: Series Cascode Configurations.

3.7 ESD MOSFET Design: Multi-Finger Design Integration of Coupling and Ballasting Techniques.

3.8 ESD MOSFET Design: Enclosed Drain Design Practice.

3.9 ESD MOSFET Interconnect Ballasting Design.

3.10 ESD MOSFET Design: Source and Drain Segmentation.

3.11 Summary and Closing Comments.

Problems.

References.

Chapter 4: Electrostatic Discharge (ESD) Design: Diode Design.

4.1 ESD Diode Design: ESD Basic.

4.2 ESD Diode Design: Anode.

4.3 ESD Diode Design: Interconnect Wiring.

4.4 ESD Diode Design: Polysilicon-Bound Diode Designs.

4.5 ESD Diode Design: n-Well Diode Design.

4.6 ESD Diode Design: nþ/p Substrate Diode Design.

4.7 ESD Diode Design: Diode String.

4.8 ESD Diode Design: Triple-Well Diodes.

4.9 ESD Design: BiCMOS ESD Design.

4.10 Summary and Closing Comments.

Problems.

References.

Chapter 5: Silicon on Insulator (SOI) ESD Design.

5.1 SOI ESD Basic Concepts.

5.2 SOI ESD Design: MOSFET with Body Contact (T-Shaped Layout).

5.3 SOI ESD Design: SOI Lateral Diode Structure.

5.4 SOI ESD Design: Buried Resistors (BR) Elements.

5.5 SOI ESD Design: SOI Dynamic Threshold MOSFET (DTMOS).

5.6 SOI ESD Design: Dual-Gate (DG) MOSFETs.

5.7 SOI ESD Design: FinFET Structure.

5.8 SOI ESD Design: Structures in the Bulk Substrate.

5.9 SOI ESD Design: SOI-To-Bulk Contact Structures.

5.10 Summary and Closing Comments.

Problems.

References.

Chapter 6: Off-Chip Drivers (OCD) and ESD.

6.1 Off-Chip Drivers (OCD).

6.2 Off-Chip Drivers: Mixed-Voltage Interface.

6.3 Off-Chip Drivers Self-Bias Well OCD Networks.

6.4 Off-Chip Drivers: Programmable Impedance (PIMP) OCD Networks.

6.5 Off-Chip Drivers: Universal OCDs.

6.6 Off-Chip Drivers: Gate-Array OCD Design.

6.7 Off-Chip Drivers: Gate Modulated Networks.

6.8 Off-Chip Driver ESD Design: Integration of Coupling and Ballasting Techniques.

6.9 Off-Chip Driver ESD Design: Substrate-Modulated Resistor-Ballasted MOSFET.

6.10 Summary and Closing Comments.

Problems.

References.

Chapter 7: Receiver Circuits and ESD.

7.1 Receivers and ESD.

7.2 Receivers and ESD.

7.3 Receivers and Receiver Evolution.

7.4 Receiver Circuits with Pseudo-Zero VT Half-Pass Transmission Gates.

7.5 Receiver Circuits with Zero Transmission Gate.

7.6 Receiver Circuits with Bleed Transistors.

7.7 Receiver Circuits with Test Functions.

7.8 Receiver With Schmitt Trigger Feedback Networks.

7.9 Bipolar Transistor Receivers.

7.10 Summary and Closing Comments.

Problems.

References.

Chapter 8: SOI ESD Circuits and Design Integration.

8.1 SOI ESD Design Integration.

8.2 SOI ESD Design: Diode Design.

8.3 SOI ESD Diode Design: Mixed Voltage Interface (MVI) Environments.

8.4 SOI ESD Networks in SOI CPU with Aluminum (Al) Interconnects.

8.5 SOI ESD Design in Copper (Cu) Interconnects.

8.6 SOI ESD Design with Gate Circuitry.

8.7 SOI and Dynamic Threshold ESD Networks.

8.8 SOI Technology and Miscellaneous ESD Issues

8.9 Summary and Closing Comments.

Problems.

References.

Chapter 9: ESD Power Clamps.

9.1 ESD Power Clamp Design Practices.

9.2 ESD Power Clamps: Diode-Based.

9.3 ESD Power Clamps: MOSFET-Based.

9.4 ESD Power Clamps: Bipolar-Based.

9.5 ESD Power Clamps: Silicon Controlled Rectifier-Based.

9.6 Summary and Closing Comments.

Problems.

References.

Index.

Read More Show Less

Customer Reviews

Be the first to write a review
( 0 )
Rating Distribution

5 Star

(0)

4 Star

(0)

3 Star

(0)

2 Star

(0)

1 Star

(0)

Your Rating:

Your Name: Create a Pen Name or

Barnes & Noble.com Review Rules

Our reader reviews allow you to share your comments on titles you liked, or didn't, with others. By submitting an online review, you are representing to Barnes & Noble.com that all information contained in your review is original and accurate in all respects, and that the submission of such content by you and the posting of such content by Barnes & Noble.com does not and will not violate the rights of any third party. Please follow the rules below to help ensure that your review can be posted.

Reviews by Our Customers Under the Age of 13

We highly value and respect everyone's opinion concerning the titles we offer. However, we cannot allow persons under the age of 13 to have accounts at BN.com or to post customer reviews. Please see our Terms of Use for more details.

What to exclude from your review:

Please do not write about reviews, commentary, or information posted on the product page. If you see any errors in the information on the product page, please send us an email.

Reviews should not contain any of the following:

  • - HTML tags, profanity, obscenities, vulgarities, or comments that defame anyone
  • - Time-sensitive information such as tour dates, signings, lectures, etc.
  • - Single-word reviews. Other people will read your review to discover why you liked or didn't like the title. Be descriptive.
  • - Comments focusing on the author or that may ruin the ending for others
  • - Phone numbers, addresses, URLs
  • - Pricing and availability information or alternative ordering information
  • - Advertisements or commercial solicitation

Reminder:

  • - By submitting a review, you grant to Barnes & Noble.com and its sublicensees the royalty-free, perpetual, irrevocable right and license to use the review in accordance with the Barnes & Noble.com Terms of Use.
  • - Barnes & Noble.com reserves the right not to post any review -- particularly those that do not follow the terms and conditions of these Rules. Barnes & Noble.com also reserves the right to remove any review at any time without notice.
  • - See Terms of Use for other conditions and disclaimers.
Search for Products You'd Like to Recommend

Recommend other products that relate to your review. Just search for them below and share!

Create a Pen Name

Your Pen Name is your unique identity on BN.com. It will appear on the reviews you write and other website activities. Your Pen Name cannot be edited, changed or deleted once submitted.

 
Your Pen Name can be any combination of alphanumeric characters (plus - and _), and must be at least two characters long.

Continue Anonymously
Sort by: Showing all of 3 Customer Reviews
  • Posted February 20, 2011

    Highly recommended to circuit designers and students

    This is one of the best books on ESD. All the major ESD building blocks and issues are fully investigated and elegantly written. A perfect balance between circuit and device is an important feature of this book. This is the second book of this series and the author obviously devoted a tremendous amount of time and effort to the writing. The treatment is comprehensive enough to make this book the textbook for an ESD course. It's worth noting that the author is a world expert on ESD and integrated circuit technologies, and was named an IEEE fellow for his contributions in these areas. It's great that he shared lots of valuable knowledge, design experience and deep insights. Chapters 3 and 4 help readers quickly gain solid understanding of the two key elements in ESD design domain: MOSFET and diodes. The chapters on driver, receiver, and power clamp help complete the knowledge of ESD building blocks. All these chapters are written from circuit design perspective rather than pure device physics. Chapters focusing on SOI are a big plus. There are plenty of helpful illustrations in this book, and the perfect number of equations to enhance readers understanding. Please consider using this as your first book to read in ESD. You will keep referring to this book many years from now. Engineers with lots of experience would find this book very useful as well.

    Was this review helpful? Yes  No   Report this review
  • Anonymous

    Posted January 24, 2008

    A very useful ESD book about ESD devices and circuits

    I have had this book for a while. This one is the second book of the author's ESD book series which cover the most comprehensive topics related to ESD protection comparing with other ESD books. It is one of the most recently published ESD books with new and updated date points and the latest developments in the field. The thing I like most is, just like the name (circuits and devices) of the book, it not only takes the ESD protection devices as topics to present all the ESD design issues, but also takes the circuit applications as topics to discuss the concerns of ESD design, which gives you the picture that only with good individual ESD protection devices, the successful full-chip ESD solution is not automatic. It is a useful book for both designers and device engineers. I always keep it at hand for my ESD design projects.

    Was this review helpful? Yes  No   Report this review
  • Anonymous

    Posted January 18, 2008

    A reviewer

    This book, ESD: Circuits and Devices, is part of a 3-book series on Electrostatic Discharge (ESD) by the same author (Steven Voldman). One of the main strengths of this series (and there are very many) is that this is very recently published with new and updated datapoints, not to mention being the only series of ESD textbook. Essentially, this means that all the latest developments in the field is published in an easy-to-understand series. In this book, Voldman writes about the design of ESD protection circuits in his unique style which is illuminating both for experts and beginners alike. I highly recommend this book series to all students of integrated circuit design and ESD.

    Was this review helpful? Yes  No   Report this review
Sort by: Showing all of 3 Customer Reviews

If you find inappropriate content, please report it to Barnes & Noble
Why is this product inappropriate?
Comments (optional)