ESD: Failure Mechanisms and Models / Edition 1

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Overview

Electrostatic discharge (ESD) failure mechanisms continue to impact semiconductor components and systems as technologies scale from micro- to nano-electronics.

This book studies electrical overstress, ESD, and latchup from a failure analysis and case-study approach. It provides a clear insight into the physics of failure from a generalist perspective, followed by investigation of failure mechanisms in specific technologies, circuits, and systems. The book is unique in covering both the failure mechanism and the practical solutions to fix the problem from either a technology or circuit methodology.

Look inside for extensive coverage on:

  • failure analysis tools, EOS and ESD failure sources and failure models of semiconductor technology, and how to use failure analysis to design more robust semiconductor components and systems;
  • electro-thermal models and technologies; the state-of-the-art technologies discussed include CMOS, BiCMOS, silicon on insulator (SOI), bipolar technology, high voltage CMOS (HVCMOS), RF CMOS, smart power,  gallium arsenide (GaAs), gallium nitride (GaN), magneto-resistive (MR) , giant magneto-resistors (GMR),  tunneling magneto-resistor (TMR),  devices; micro electro-mechanical (MEM) systems, and  photo-masks and reticles; 
  • practical methods to use failure analysis for the understanding of ESD circuit operation, temperature analysis, power distribution, ground rule development, internal bus distribution, current path analysis, quality metrics, (connecting the theoretical to the practical analysis);
  • the failure of each key element of a technology from passives, active elements to the circuit, sub-system to package, highlighted by case studies of the elements, circuits and system-on-chip (SOC) in today’s  products. 

ESD: Failure Mechanisms and Models is a continuation of the author’s series of books on ESD protection. It is an essential reference and a useful insight into the issues that confront modern technology as we enter the Nano-electronic era.

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Product Details

  • ISBN-13: 9780470511374
  • Publisher: Wiley
  • Publication date: 9/15/2009
  • Edition number: 1
  • Pages: 408
  • Sales rank: 1,224,805
  • Product dimensions: 6.80 (w) x 9.80 (h) x 1.10 (d)

Meet the Author

Dr Steven H. Voldman received his B.S. in Engineering Science from the University of Buffalo (1979); M.S. EE (1981) and Electrical Engineer Degree (1982) from M.I.T; MS Engineering Physics (1986) and Ph.D EE (1991) from the University of Vermont under IBM's Resident Study Fellow Program. At M.I.T, he worked as a member of the M.I.T. Plasma Fusion Center, and the High Voltage Research Laboratory (HVRL). At IBM, as a reliability device engineer, his work include pioneering work in bipolar/ CMOS SRAM alpha particle and cosmic ray SER simulation, MOSFET gate-induced drain leakage (GIDL) mechanism, hot electron, epitaxy/well design, CMOS latchup, and ESD. Since 1986, he has been responsible for defining the IBM ESD/latchup strategy for CMOS, SOI, BiCMOS and RF CMOS and SiGe technologies. He has authored ESD and latchup publications in the area of MOSFET Scaling, device simulations, copper, low-k, MR heads, CMOS, SOI , Sage and SiGeC technology. Voldman served as SEMATECH ESD Working Group Chairman (1996-2000), ESD Association General Chairman and Board of Directors, International Reliability Physics (IRPS) ESD/Latchup Chairman, International Physical and Failure Analysis (IPFA) Symposium ESD Sub-Committee Chairman, ESD Association Standard Development Chairman on Transmission Line Pulse Testing, ESD Education Committee, and serves on the ISQED Committee, Taiwan ED Conference (T-ESDC) Technical Program Committee. Voldman has provided ESD lectures for universities (e.g. MIT Lecture Series, Taiwan National Chiao-Tung University, and Singapore Nanyang Technical University). He is a recipient of over 125 US patents, over 100 publications, and also provides talks on patenting, and invention. He has been featured in EE Times, Intellectual Property Law and Business and authored the first article on ESD phenomena for the October 2002 edition of Scientific American entitled Lightening Rods for Nanostructures, and Pour La Science, Le Scienze, and Swiat Nauk international editions. Dr. Voldman was recently accepted as the first IEEE Fellow for ESD phenomena in semiconductors for ' contributions to electrostatic discharge protection CMOS, SOI and SiGe technologies'.

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Table of Contents

About the Author.

Preface.

Acknowledgments.

1 Failure Analysis and ESD.

1.1 Introduction.

1.2 ESD Failure: How Do Micro-electronic Devices Fail?.

1.3 Sensitivity of Semiconductor Components.

1.4 How Do Semiconductor Chips Fail––Are the Failures Random or Systematic?.

1.5 Closing Comments and Summary.

Problems.

References.

2 Failure Analysis Tools, Models, and Physics of Failure.

2.1 FA Techniques for Evaluation of ESD Events.

2.2 FA Tools.

2.3 ESD Simulation: ESD Pulse Models.

2.4 Electro-Thermal Physical Models.

2.5 Statistical Models for ESD Prediction.

2.6 Closing Comments and Summary.

Problems.

References.

3 CMOS Failure Mechanisms.

3.1 Tables of CMOS ESD Failure Mechanisms.

3.2 LOCOS Isolation-Defined CMOS.

3.3 Shallow Trench Isolation (STI).

3.4 Polysilicon-Defined Devices.

3.5 Lateral Diode with Block Mask.

3.6 MOSFETs.

3.7 Resistors.

3.8 Interconnects: Wires, Vias, and Contacts.

3.9 ESD Failure in CMOS Nanostructures.

3.10 Closing Comments and Summary.

Problems.

References.

4 CMOS Circuits: Receivers and Off-Chip Drivers.

4.1 Tables of CMOS Receiver and OCD ESD Failure Mechanisms.

4.2 Receiver Circuits.

4.3 Receivers Circuits with ESD Networks.

4.4 Receiver Circuits with Half-Pass Transmission Gate.

4.5 Receiver with Full-Pass Transmission Gate.

4.6 Receiver, Half-Pass Transmission Gate, and Keeper Network.

4.7 Receiver Circuit with Pseudo-zero VT Half-Pass Transmission Gate.

4.8 Receiver with Zero VT Transmission Gate.

4.9 Receiver Circuits with Bleed Transistors.

4.10 Receiver Circuits with Test Functions.

4.11 Receiver with Schmitt Trigger Feedback Networks.

4.12 Off-Chip Drivers.

4.13 Single NFET Pull-down OCD.

4.14 Series Cascode MOSFETs.

4.15 I/O Design Considerations and ESD Parasitic Failure Mechanisms.

4.16 Closing Comments and Summary.

Problems.

References.

5 CMOS Integration.

5.1 Table of CMOS Integration ESD Failure Mechanisms.

5.2 Architecture and Design Synthesis-Related Failures.

5.3 Alternate Current Loop.

5.4 Chip Capacitance.

5.5 ESD Power Clamps.

5.6 Intra- and Inter-domain ESD Protection.

5.7 Split Ground Configurations.

5.8 Mixed Voltage Interface.

5.9 Mixed Signal Interface.

5.10 Inter-domain Signal Line ESD Failures.

5.11 Decoupling Capacitors.

5.12 System Clock and Phase-Locked Loop.

5.13 Fuse Networks.

5.14 Bond Pads.

5.15 MOSFET Gate Structure.

5.16 Fill Shapes.

5.17 No Connects.

5.18 Test Circuitry.

5.19 Multi-chip Systems.

5.20 CMOS Latchup Failures.

5.21 Closing Comments and Summary.

Problems.

References.

6 SOI ESD Failure Mechanisms.

6.1 Tables of SOI Device and Integration ESD Failure Mechanisms.

6.2 SOI N-channel MOSFETs.

6.3 SOI Diodes.

6.4 SOI Buried Resistors.

6.5 SOI Failure Mechanisms in 150 nm Technology.

6.6 SOI ESD Failure Mechanisms in 45 nm Technology.

6.7 SOI ESD Failure Mechanisms in 32 nm Technology.

6.8 SOI ESD Failure Mechanisms in 22 nm Technology and the Future.

6.9 SOI Design Synthesis and ESD Failure Mechanisms.

6.10 SOI Integration: ESD Failure Mechanisms.

6.11 Closing Comments and Summary.

Problems.

References.

7 RF CMOS and ESD.

7.1 Tables of RF CMOS ESD Failure Mechanisms.

7.2 RF MOSFET.

7.3 RF Shallow Trench Isolation Diode.

7.4 RF Polysilicon Gated Diode.

7.5 Silicon-Controlled Rectifier.

7.6 Schottky Barrier Diodes.

7.7 Capacitors.

7.8 Resistors.

7.9 Inductors.

7.10 Examples of RF ESD Circuit Failure Mechanisms.

7.11 Closing Comments and Summary.

Problems.

Reference.

8 Micro-electromechanical Systems.

8.1 Table of MEM Failure Mechanisms.

8.2 Electrostatically Actuated Devices.

8.3 Micro-mechanical Engines.

8.4 Torsional Ratcheting Actuator.

8.5 Electromagnetic Micro-power Generators.

8.6 MEM Inductors.

8.7 Electrostatically Actuated Variable Capacitor.

8.8 Micro-mechanical Switches.

8.9 RF MEM Switch.

8.10 Micro-mechanical Mirrors.

8.11 Electrostatically Actuated Torsional Micro-mirrors.

8.12 Closing Comments and Summary.

Problems.

References.

9 Gallium Arsenide.

9.1 Tables of GaAs-Based ESD Failure Mechanisms.

9.2 GaAs Technology.

9.3 GaAs Energy-to-failure and Power-to-failure.

9.4 GaAs ESD Failures in Active and Passive Elements.

9.5 GaAs HBT Devices.

9.6 GaAs HBT-Based Passive Elements.

9.7 GaAs PHEMT Devices.

9.8 GaAs Power Amplifiers.

9.9 InGaAs.

9.10 Gallium Nitride.

9.11 InP and ESD.

9.12 Closing Comments and Summary.

Problems.

References.

10 Smart Power, LDMOS, and BCD Technology.

10.1 Tables of LDMOS ESD Failure Mechanisms.

10.2 LOCOS-Defined LDMOS Devices.

10.3 STI-Defined LDMOS Devices.

10.4 STI-Defined Isolated LDMOS Transistors.

10.5 LDMOS Transistors: ESD Electrical Measurements.

10.6 LDMOS-Based ESD Networks.

10.7 LDMOS ESD Failure Mechanisms.

10.8 LDMOS Transistor Design Enhancement.

10.9 Latchup Events in LDMOS and BCD Technology.

10.10 Closing Comments and Summary.

Problems.

References.

11 Magnetic Recording.

11.1 Tables of Magnetic Recording Failure Mechanisms.

11.2 MR Heads.

11.3 Inductive Heads.

11.4 GMR Heads.

11.5 TMR Heads.

11.6 ESD Solutions.

11.7 Closing Comments and Summary.

Problems.

References.

12 Photo-masks and Reticles: Failure Mechanisms.

12.1 Table of Photo-masks ESD Failure Mechanisms.

12.2 Photo-mask Failure Mechanisms.

12.3 Photo-mask Inspection Tools.

12.4 Photo-mask ESD Characterization.

12.5 Electrical Breakdown Versus Gap Spacing.

12.6 Electrical Breakdown in Air: The Townsend Model.

12.7 Electric Breakdown in Air: Toepler’s Spark Law.

12.8 Air Breakdown: The Paschen Breakdown Model.

12.9 Paschen Curve Versus Reticle Breakdown Plot.

12.10 Electrical Model of Photo-mask Breakdown.

12.11 ESD Latent Damage.

12.12 ESD Damage for Single Versus Multiple Events.

12.13 ESD Damage to Anti-reflective Coating.

12.14 ESD Solutions in Photo-masks.

12.15 Closing Comments and Summary.

Problems.

References.

Index.

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Sort by: Showing all of 3 Customer Reviews
  • Posted February 15, 2011

    Highly recommended - must-read for ESD designers

    I'm an ESD engineer in the semiconductor industry. I have read many of the ESD books published in the past 20 years, but did not find one dedicated to this topic until this book was published. This is a very important topic for ESD and reliability engineering. So I'm sure that there are many engineers like me who have been waiting for such a book for a long time. This book is very well written like all the other books in this series by Dr. Voldman, who is an IEEE fellow and top expert in the world. The book starts from basic knowledge and then gradually goes into great details. The subject is covered thoroughly and comprehensively. Moreover, there are several reasons that make this book particularly valuable to a wide range of readers from new engineers/students to industry veterans. The best way to learn about failure mechanism is not only by reading the theories, but also studying the pictures from real failure analysis experiments. Such experiments are very specialized and costly, therefore illustrations are more difficult to acquire. In this book, however, there are many high-quality pictures taken from advanced microscopes. Instead of reading the descriptions about how IC fails under ESD and what happens afterward, readers can see what the failure sites look like in reality and learn the failure signatures. While this book is about mechanisms and models, there aren't overwhelmingly complicated equations. Some key equations are included only when absolutely needed. For most readers, especially students and enthusiastic novice readers, the last thing they want is to be discouraged by tedious derivations that don't help directly improve their understanding. With the appropriate number of equations and analysis, reading this book has been a pleasant learning experience. The reference sections are quite complete and very up-to-date. In addition to the carefully chosen classic references, there are many recent references including even papers published in 2008 and 2009, which indicates that the author has made a great effort to keep the materials updated. Many real-world examples in advanced technology nodes are illustrated. This is a big plus considering the discussed field is rapidly advancing. The second half of this book covers many advanced topics in great detail, which is hard to find elsewhere. For example, SOI failures, MEMS, GaAs, Smart Power, Magnetic recording and so on. While some of these topics can be found in conference proceedings, the methodical treatment in this book makes the learning most efficient. I'm glad to have found this book as I realize how critical it is to understand failures mechanisms. Considering the uniqueness of the book's coverage, I believe it is a must-read for ESD and reliability engineers.

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  • Posted May 10, 2010

    A good book about ESD failure mechanisms

    I got this book recently. A very useful book which addresses ESD failure mechanisms comprehensively and systematically. It discusses ESD failure mechanisms in "old" technologies as well as updating the modifications to the state-of-the-art technologies, covering a wide spectrum of technologies from CMOS, RF CMOS, SOI, smart power, GaAs, magneto-resistive heads, tunneling magneto-resistive heads, MEM systems, to photo-masks and reticles. This book starts with the fundamentals and concepts of ESD failure and basics of failure analysis tools, then proceeds to the failure mechanisms of all kinds of FEOL components and BEOL interconnects along with the CMOS technology scaling from 2.0 um to 32 nm, which provides a whole view of the evolvement of ESD failure mechanisms. Further, the book discusses the failure mechanisms associated with CMOS peripheral circuits and chip architecture and design synthesis, focusing on how to build more ESD and EOS robust components and systems, which is what I like most of this book. For example, the author analyses the current paths and failure mechanisms of all the different receiver networks. The understanding can be transferred to other circuits and peripheral devices.

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  • Posted January 30, 2010

    Essential tool/reference for the working Failure Analysis professional.

    The text is effective in relating the physical damage that is observed to the electrical mechanisms that arise during an ESD event. Once the mechanisms are understood changes in the technology and/or the surrounding circuitry can be made that will improve the product and make it more robust to similar overstress exposures.

    The unique perspective that this book offers is that the it provides an explanation more from a failure analyst perspective lessening the focus from a semiconductor physics standpoint. This work provides insights into the types of analysis that can be performed and relating those finding to actual case studies across a wide variety of technologies.

    In summary, as a failure analysis professional this book will be referenced as routinely as an interpretative aid in my day to day analysis work. Highly recommended.

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