Functional Design Errors in Digital Circuits: Diagnosis Correction and Repair / Edition 1

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Overview

Functional Design Errors in Digital Circuits Diagnosis covers a wide spectrum of innovative methods to automate the debugging process throughout the design flow: from Register-Transfer Level (RTL) all the way to the silicon die. In particular, this book describes: (1) techniques for bug trace minimization that simplify debugging; (2) an RTL error diagnosis method that identifies the root cause of errors directly; (3) a counterexample-guided error-repair framework to automatically fix errors in gate-level and RTL designs; (4) a symmetry-based rewiring technology for fixing electrical errors; (5) an incremental verification system for physical synthesis; and (6) an integrated framework for post-silicon debugging and layout repair. The solutions provided in this book can greatly reduce debugging effort, enhance design quality, and ultimately enable the design and manufacture of more reliable electronic devices.

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Product Details

  • ISBN-13: 9781402093647
  • Publisher: Springer Netherlands
  • Publication date: 12/9/2008
  • Series: Lecture Notes in Electrical Engineering Series , #32
  • Edition description: 2009
  • Edition number: 1
  • Pages: 200
  • Product dimensions: 6.40 (w) x 9.30 (h) x 0.80 (d)

Meet the Author

Winner of the EDAA (European Design Automation Association) Outstanding Monograph Award in the Verification section. Co-authors Bertacco and Markov are existing Springer authors

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Table of Contents

List of Figures

List of Tables

Pt. I Background and Prior Art

1 Introduction 3

2 Current Landscape in Design and Verification 13

3 Finding Bugs and Repairing Circuits 25

Pt. II FogClear Methodologies and Theoretical Advances in Error Repair

4 Circuit Design and Verification Methodologies 37

5 Counterexample-Guided Error-Repair Framework 43

6 Signature-Based Resynthesis Techniques 51

7 Symmetry-Based Rewiring 57

Pt. III FogClear Components

8 Bug Trace Minimization 77

9 Functional Error Diagnosis and Correction 105

10 Incremental Verification for Physical Synthesis 133

11 Post-Silicon Debugging and Layout Repair 147

12 Methodologies for Spare-Cell Insertion 167

13 Conclusions 183

References 187

Index 199

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