Great Lakes 6th Symposium on VLSI

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Fifty-one selected proceedings papers written by computer researchers in the Great Lakes, region and also by international contributors, representing the core discussions of the March 1996 symposium at Iowa State University. The VLSI based presentations focus on current trends and methodologies, covering physical design, verification and synthesis, testing, low power design, high-level synthesis and architecture, and circuit design. Lacks an index. Annotation c. Book News, Inc., Portland, OR (
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Product Details

  • ISBN-13: 9780818675027
  • Publisher: IEEE Computer Society Press
  • Publication date: 1/28/1996
  • Pages: 300

Table of Contents

Message from the Program Co-chairs
Message from the Steering Chair
Steering Committee
Program Committee
Loop-List Scheduling for Heterogeneous Functional Units 2
Synthesis of Real-Time Recursive DSP Algorithms Using Multiple Chips 8
Resource-Constrained Algebraic Transformation for Loop Pipelining 14
A Global Mode Instruction Minimization Technique for Embedded DSPRs 18
A 1.0ns 64-bits GaAs Adder using Quad-Tree Algorithm 24
FPGA-Based High Performance Page Layout Segmentation 29
A Reprogrammable FPGA-Based ATM Traffic Generator 35
Software Fault Tolerance Using Dynamically Reconfigurable FPGAs 39
A New Faster Algorithm for Iterative Placement Improvement 44
An Accurate Interconnection Length Estimation for Computer Logic 50
A Minimum-Area Floorplanning Algorithm for Mixed Block and Cell Designs 56
A New Model for General Connectivity and its Application to Placement 60
A Parameterized Index-Generator for the Multi-Dimensional Interleaving Optimization 66
A High Speed VLSI Architecture for Scaleable ATM Switches 72
A Design Exploration Environment 77
A Parametrical Architecture for Reed-Solomon Decoders 81
A Provably Good Moat Routing Algorithm 86
On Locally Optimal Breaking of Complex Cyclic Vertical Constraints in VLSI Channel Routing 92
Chip Pad Migration is a Key Component to High Performance MCM Design 96
An Optimal ILP Formulation for Minimizing the Number of Feedthrough Cells in Standard Cell Placement 100
Formal Verification of an ATM Switch Fabric Using Multiway Decision Graphs 106
Boolean Function Representation Using Parallel-Access Diagrams 112
Logic Synthesis for Testability 118
Self-Timed Mesochronous Interconnection for High-Speed VLSI Systems 122
Least Upper Bounds on the Sizes of Symmetric Variable Order Based OBDDs 126
Performance-Driven Interconnect Global Routing 132
Recent Developments in Performance Driven Steiner Routing: An Overview 137
Clock Buffer Placement Algorithm for Wire-Delay-Dominated Timing Model 143
Simultaneous Routing and Buffer Insertion for High Performance Interconnect 148
Timing and Power Optimization by Gate Sizing Considering False Path 154
Exact Computation of the Entropy of a Logic Circuit 162
CMOS Transistor Sizing for Minimization of Energy-Delay Product 168
Low-Power Implementation of Discrete Cosine Transform 174
Some Issues in Gray Code Addressing 178
A Hierarchical Approach for Power Reduction in VLSI Chips 182
TROY: A Tree-Based Approach to Logic Synthesis and Technology Mapping 188
Transistor Chaining in CMOS Leaf Cells of Planar Topology 194
Partitioning Algorithms for Corner Stitching 200
Test Generation for Networks of Interacting FSMs Using Symbolic Techniques 208
Input Pattern Classification for Transistor Level Testing of Bridging Faults in BiCMOS Circuits 214
Efficient Delay Test Generation for Modular Circuits 220
Design and VLSI Implementation of a Unified Synapse-Neuron Architecture 228
Rapid Prototyping for Fuzzy Systems 234
A Modular Architecture for Real Time HDTV Motion Estimation with Large Search Range 240
A VLSI Interconnection Network Router Using a D-CAM with Hidden Refresh 246
A High-Speed, Real-to-Quadrature Converter with Filtering and Decimation 252
A CMOS VLSI Implementation of an NxN Multiplexing Circuitry for ATM Applications 256
A 3V-50MHz Analog CMOS Current-Mode High Frequency Filter with a Negative Resistance Load 260
Delay Hazards in Complex Gate Based Speed Independent VLSI Circuits 266
Macromodeling C- and RC-loaded CMOS Inverters for Timing Analysis 272
On Verifying the Correctness of Retimed Circuits 277
On Double Transition Faults as a Delay Fault Model 282
Improving Circuit Testability by Clock Control 288
An Efficient Multiple Scan Chain Testing Scheme 294
Index of Authors 299
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