Hierarchical Modeling for VLSI Circuit Testing / Edition 1by Debashis Bhattacharya, John P. Hayes
Pub. Date: 12/31/1989
Publisher: Springer US
Test generation is one of the most difficult tasks facing the designer of complex VLSI-based digital systems. Much of this difficulty is attributable to the almost universal use in testing of low, gate-level circuit and fault models that predate integrated circuit technology. It is long been recognized that the testing prob lem can be alleviated by the use of… See more details below
Test generation is one of the most difficult tasks facing the designer of complex VLSI-based digital systems. Much of this difficulty is attributable to the almost universal use in testing of low, gate-level circuit and fault models that predate integrated circuit technology. It is long been recognized that the testing prob lem can be alleviated by the use of higher-level methods in which multigate modules or cells are the primitive components in test generation; however, the development of such methods has proceeded very slowly. To be acceptable, high-level approaches should be applicable to most types of digital circuits, and should provide fault coverage comparable to that of traditional, low-level methods. The fault coverage problem has, perhaps, been the most intractable, due to continued reliance in the testing industry on the single stuck-line (SSL) fault model, which is tightly bound to the gate level of abstraction. This monograph presents a novel approach to solving the foregoing problem. It is based on the systematic use of multibit vectors rather than single bits to represent logic signals, including fault signals. A circuit is viewed as a collection of high-level components such as adders, multiplexers, and registers, interconnected by n-bit buses. To match this high-level circuit model, we introduce a high-level bus fault that, in effect, replaces a large number of SSL faults and allows them to be tested in parallel. However, by reducing the bus size from n to one, we can obtain the traditional gate-level circuit and models.
- Springer US
- Publication date:
- The Springer International Series in Engineering and Computer Science, #89
- Edition description:
- Product dimensions:
- 9.21(w) x 6.14(h) x 0.44(d)
Table of Contents1 Introduction.- 1.1 Background.- 1.2 Prior Work.- 1.2.1 Test Generation for Combinational Circuits.- 1.2.2 Test Generation for Sequential Circuits.- 1.2.3 High-level Test Generation.- 1.2.4 Fault Simulation.- 1.2.5 Design for Testability.- 1.3 Outline.- 2 Circuit and Fault Modeling.- 2.1 Vector Sequence Notation.- 2.2 Circuit and Fault Models.- 2.2.1 Circuit Model.- 2.2.2 Fault Model.- 2.3 Case Study: k-Regular Circuits.- 3 Hierarchical Test Generation.- 3.1 Vector Cubes.- 3.2 Test Generation.- 3.2.1 Repetitive Circuits.- 3.2.2 Pseudo-Sequential Circuits.- 3.2.3 High-Level Test Generation Algorithm.- 3.3 Implementation and Experimental Results.- 3.3.1 Circuit Description.- 3.3.2 Data Structures.- 3.3.3 Program Structure.- 3.3.4 Experimental Results.- 4 Design for Testability.- 4.1 Ad Hoc Techniques.- 4.1.1 Array-Like Circuits.- 4.1.2 Tree-Like Circuits.- 4.2 Level Separation (LS) Method.- 4.2.1 Functions Realizable by One-Dimensional ILA’s.- 4.2.2 Functions Realizable by Two-Dimensional ILA’s.- 4.3 Case Study: ALU.- 5 Concluding Remarks.- 5.1 Summary.- 5.2 Future Directions.- Appendix A: Proofs of Theorems.- A.1 Proof of Theorem 3.2.- A.2 Proof of Theorem 3.3.- A.3 Proof of Theorem 4.1.
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