High-Speed CMOS Circuits for Optical Receivers / Edition 1

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The exponential growth of the number of internet nodes has suddenly created a widespread demand for high-speed optical and electronic devices, circuits, and systems. The new optical revolution has replaced modular, general-purpose building blocks by end-to-end solutions. Greater levels of integration on a single chip enable higher performance and lower cost. The mainstream VLSI technologies such as BiCmos and CMOS continue to take over the territories thus far claimed by GaAs and InP devices. This calls for an up-to-date book describing the design of high-speed electronic circuits for optical communication using modern techniques in a low-cost CMOS process. High-Speed CMOS Circuits for Optical Receivers covers the design of the world's first and second 10 Gb/s clock and data recovery circuits fabricated in a pure CMOS process. The second prototype meets some of the critical requirements recommended by the SONET OC-192 standard. The clock and data recovery circuits consume a power several times lower than in prototypes built in other fabrication processes. High-Speed CMOS Circuits for Optical Receivers describes novel techniques for implementation of such high-speed, high-performance circuits in a pure CMOS process. High-Speed CMOS Circuits for Optical Receivers is written for researchers and students interested in high-speed and mixed-mode circuit design with focus on CMOS circuit techniques. Designers working on various high-speed circuit projects for data communication, including optical com., giga bit ethernet will also find it of interest.

The new optical revolution has replaced modular, general-purpose building blocks by end-to-end solutions. Greater levels of integration on a single chip enable higher performance and lower cost. The mainstream VLSI technologies such as BiCmos and CMOS continue to take over the territories thus far claimed by GaAs and InP devices.

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Editorial Reviews

From The Critics
Following an overview of the fiber optic network, this volume describes clock and data recovery (CDR) architectures, the design of the world's first and second 10-Gb/s (gigabytes per second) CDR circuits to support the exponential growth of the Internet, and the CMOS processes that now dominate fabrication of the electronic interface in optical systems. The authors conclude that the CDR circuit remains the key to optical receivers, and that advances in the CMOS process will further improve performance and lower costs. Includes supporting diagrams and 53 references. Savoj works for a technology company. Razavi is at the U. of California, Los Angeles. Annotation c. Book News, Inc., Portland, OR (booknews.com)
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Product Details

  • ISBN-13: 9780792373889
  • Publisher: Springer US
  • Publication date: 5/31/2001
  • Edition description: 2001
  • Edition number: 1
  • Pages: 124
  • Product dimensions: 0.44 (w) x 6.14 (h) x 9.21 (d)

Meet the Author

Jafar Savoj Transpectrum Technologies, Los Angeles, CA, USA.

Behzad Razavi University of California, Los Angeles, USA

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Read an Excerpt

Chapter 5


This chapter describes the design and experimental results of a 10Gb/s CMOS phase-locked clock and data recovery circuit. The circuit incorporates an interpolating voltage-controlled oscillator and a half-rate phase detector. The phase detector provides a linear characteristic while retiming and demultiplexing the data with no systematic phase offset. Fabricated in a 0.18-tim CMOS technology in an area of 1.1 x 0.9 mm2, the circuit exhibits an rms jitter of 1 ps, and a peak-to-peak jitter of 14.5 ps in the recovered clock and a bit error rate of 1.28 x 10-6, with random data input of length 223 - 1. The power dissipation is 72 mW from a 2.5-V supply.

The next section describes the CDR architecture and its design issues. The following sections present the design of the building blocks and the description of the experimental results.

1. Architecture

The choice of the CDR architecture is primarily determined by the speed and supply voltage limitations of the technology as well as the power dissipation and jitter requirements of the system.

In a generic CDR circuit, shown in Fig. 5.1, the phase detector compares the phase of the incoming data to the phase of the clock generated by the voltage-controlled oscillator (VCO), producing an error that is proportional to the phase difference between its two inputs. The error is then applied to a charge pump and a low-pass filter so as to generate the oscillator control voltage. The clock signal also drives a decision circuit, thereby retiming the data and reducing its jitter.

If attempted in a 0.18-pm CMOS technology, the architecture of Fig. 5.1 poses severe difficulties for 10-Gb/s operation. Although exploiting aggressive device scaling, the CMOS process used in this work provides marginal performance for such speeds. For example, even simple digital latches or three-stage ring oscillators fail to operate reliably at these rates. These issues make it desirable to employ a "half-rate" CDR architecture, where the VCO runs at a frequency equal to half of the input data rate. The concept of half-rate clock has been used in [44]-[47]. However, [44] and [45] incorporate a bang-bang phase detector (PD), possibly creating large ripple on the control line of the oscillator and hence high jitter. The circuit reported in [46] inherently has a smaller output jitter as a result of using a linear phase detector, but it fails to operate at speeds above 6 Gb/s in 0.18-pm CMOS technology. The circuit of [47] benefits from a new linear phase detection scheme, but it may not operate properly with certain data patterns.

Another critical issue in the architecture of Fig. 5.1 relates to the inherently unequal propagation delays for the two inputs of the phase detector: Most phase detectors that operate properly with random data (e.g., a D flipflop) are asymmetric with respect to the data and clock inputs, thereby introducing a systematic skew between the two in phaselock condition. Since it is difficult to replicate this skew in the decision circuit, the generic CDR architecture suffers from a limited phase margin - unless the raw speed of the technology is much higher than the data rate.

The problem of the skew demands that phase detection and data regeneration occur in the same circuit such that the clock still samples the data at the midpoint of each bit even in the presence of a finite skew. For example the Hogge PD [32] automatically sets the clock phase to the optimum point in the data eye (but it fails to operate properly with a half-rate clock).

The above considerations lead to the CDR architecture shown in Fig. 5.2. Here, a half-rate phase detector produces an error proportional to the phase difference between the 10-Gb/s data stream and the 5-GHz output of the VCO. Furthermore, the PD automatically retimes and demultiplexes the data, generating two 5-Gb/s sequences D5GA and D5GB. Although the focus of this work is point-to-point communications, a fullrate retimed output, D1oG, is also generated to produce flexibility in testing and exercise the ultimate speed of the technology. The VCO has both fine and coarse control lines, the latter allowing inclusion of a frequency-locked loop in future implementations.

In this chapter, a new approach to performing linear phase detection using a half-rate clock is described. Owing to its simplicity, this technique achieves both a high speed and low power dissipation while minimizing the ripple on the oscillator control voltage.

It is interesting to note that half-rate architectures do suffer from one drawback: the deviation of the clock duty cycle from 50% translates to bimodal jitter. As depicted in Fig. 5.3, since both clock edges sample the data waveform, the clock duty cycle distortion pushes both edges away from the midpoint of the bits. Typical duty cycle correction techniques used at lower speeds are difficult to apply here as they suffer from significant dynamic mismatches themselves. Thus special attention is paid to the symmetry in the layout to minimize bimodal jitter.

Another important aspect of CDR design is the leakage of data transitions to the oscillator. In Fig. 5.2, such leakage arises from (1) capacitive feedthrough from Din, to CK in the phase detector, (2) capacitive feedthrough from D5GA and D5Gg to CK through the multiplexer, and (3) coupling of D1oG to the oscillator through the substrate. To minimize these effects, the VCO is followed by an isolation buffer and all of the building blocks incorporate fully differential topologies....

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Table of Contents

List of Figures. List of Tables. Preface. 1. Introduction. 2. TIAs and Limiters. 3. Clock and Data Recovery Architectures. 4. A CMOS Interface for Detection of 1.2-GB/S RZ Data. 5. A 10-GB/S Linear Half-Rate CMOS CDR Circuit. 6. A 10-GB/S CMOS CDR Circuit with Wide Capture Range. 7. Conclusion. References. Index.
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