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HyperTransport (HT) technology promises to revolutionize connectivity for computers, servers, embedded systems, and networking and tele-communications equipment. It is a high-speed, low latency, point-to-point, packetized link that enables chips to transfer data at peak rates of up to 12.8 Gigabytes per second, far greater than existing bus technologies. Furthermore, HyperTransport improves reliability and reduces board design complexity. It is scalable and compatible with ...
HyperTransport (HT) technology promises to revolutionize connectivity for computers, servers, embedded systems, and networking and tele-communications equipment. It is a high-speed, low latency, point-to-point, packetized link that enables chips to transfer data at peak rates of up to 12.8 Gigabytes per second, far greater than existing bus technologies. Furthermore, HyperTransport improves reliability and reduces board design complexity. It is scalable and compatible with legacy PC buses, SNA, and PCI.
HyperTransport System Architecture provides a comprehensive, technical guide to HyperTransport technology. It opens with an overview of HT systems, highlighting the technology's fundamental principles, basic architecture, and its many advantages. The book goes on to detail all facets of HyperTransport systems, including the protocol, I/O, routing, configuration, and more. It also features important performance considerations and addresses critical compatibility issues.
Essential topics covered include:
A chapter is dedicated to transaction examples illustrating the practical application of HyperTransport technology.
A MindShare PC System Architecture Series book, HyperTransport System Architecture provides complete, authoritative, and detailed information necessary for developers, networking professionals, and anyone interested in implementing and deploying HT systems.
MindShare's PC System Architecture Series is a crisply written and comprehensive set of guides to the most important PC hardware standards. Books in the series are intended for use by hardware and software designers, programmers, and support personnel. Each title explains the architecture, features, and operations of systems built using one particular type of chip or hardware specification.
About This Book.
I. OVERVIEW OF HYPERTRANSPORT.
Introduction to HyperTransport.
HT Architectural Overview.
II. HYPERTRANSPORT CORE TOPICS.
Error Detection And Handling.
Reset & Initialization.
III. HYPERTRANSPORT OPTIONAL TOPICS.
HT Power Management.
IV. HYPERTRANSPORT LEGACY SUPPORT.
X86 CPU Compatibility.
The MindShare Architecture book series currently includes the books listed below. Rather than duplicating common information in each book, the series uses the building-block approach. Generally speaking, ISA System Architecture is the core book upon which the others build. In a sense, it is a PC-compatibility book. The entire book series is published by Addison-Wesley.
The reader should keep in mind that MindShare's book series often details rapidly evolving technologies. That being the case, it should be recognized that the book is a "snapshot" of the state of the technology at the time the book was completed. We make every attempt to produce our books on a timely basis, but the next revision of the specification is not introduced in time to make necessary changes.
At the time of this writing, the HyperTransport I/O Link Specification Revision 1.04 is released. The 1.04 revision of the specification does not deal with the networking extensions but much of the work on the HyperTransport 1.05 and 1.1 revisions has been done by the HyperTransport Technical Working Group, and quite a bit of preliminary information on this important addition to the protocol has been released. Some of the more important additions to these specifications are summarized in this book. Please check the MindShare Web site (www.mindshare.com) for supplemental information, updates, and errata.
This book is intended for use by hardware and software design and support personnel. The tutorial approach taken may also make it useful to technical personnel not directly involved design, verification, and other support functions.
It is recommended that the reader has a reasonable background in PC architecture, including experience or knowledge of an I/O bus and related protocol. The MindShare publication entitled ISA System Architecture focuses on various aspects of PCI architecture and provides the necessary background.
Topics covered in this book and the flow of the book are as follows:
Part 1: Overview of HyperTransport
HyperTransport is a trademark of the HyperTransport Consortium. This book takes the liberty of abbreviating HyperTransport as "HT" to improve readability.
All hex numbers are followed by a lower case "h." For example:
All binary numbers are followed by a lower case "b." For example:
1000 1001 1111 0010b
Numbers without any suffix are decimal. When required for clarity, decimal numbers are followed by a lower case "d." Examples:
This book uses the following terminology regarding quantities of data:
8-bits = 1 byte
16-bits = 2 bytes, Word
32-bits = 4 bytes, Double Word, Dword, or DW
64-bits = 8 bytes, Quad Word, Qword, or QW
This book represents bit with lower case "b" and bytes with an upper case "B."For example:
Megabits/second = Mb/s
Megabytes/second = MB/s
Groups of signals or bits are represented with the high-order bits first followed by the low-order bits and enclosed by brackets. For example:
Signals that are active low are followed by #, as in RESET#. Active high signalshave no suffix following the signal, as in PWROK.
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