Integrated Circuit Design: Power and Timing Modeling, Optimization and Simulation: 10th International Workshop, PATMOS 2000, Göttingen, Germany, September 13-15, 2000 Proceedings / Edition 1

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This book constitutes the refereed proceedings of the 10th Internation al Workshop on Power and Timing Modeling, Optimization and Simulation, PATMOS 2000, held in Goettingen, Germany in September 2000. The 33 re vised full papers presented were carefully reviewed and selected for i nclusion in the book. The papers are organized in sections on RTL powe r modeling, power estimation and optimization, system-level design, tr ansistor level design, asynchronous circuit design, power efficient te chnologies, design of multimedia processing applications, adiabatic de sign and arithmetic modules, and analog-digital circuit modeling.

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Product Details

  • ISBN-13: 9783540410683
  • Publisher: Springer Berlin Heidelberg
  • Publication date: 10/13/2000
  • Series: Lecture Notes in Computer Science Series, #1918
  • Edition description: 2000
  • Edition number: 1
  • Pages: 338
  • Product dimensions: 9.21 (w) x 6.14 (h) x 0.74 (d)

Table of Contents

Opening.- Constraints, Hurdles and Opportunities for a Successful European Take-Up Action.- RTL Power Modeling.- Architectural Design Space Exploration Achieved through Innovative RTL Power Estimation Techniques.- Power Models for Semi-autonomous RTL Macros.- Power Macro-Modelling for Firm-Macro.- RTL Estimation of Steering Logic Power.- Power Estimation and Optimization.- Reducing Power Consumption through Dynamic Frequency Scaling for a Class of Digital Receivers.- Framework for High-Level Power Estimation of Signal Processing Architectures.- Adaptive Bus Encoding Technique for Switching Activity Reduced Data Transfer over Wide System Buses.- Accurate Power Estimation of Logic Structures Based on Timed Boolean Functions.- System-Level Design.- A Holistic Approach to System Level Energy Optimization.- Early Power Estimation for System-on-Chip Designs.- Design-Space Exploration of Low Power Coarse Grained Reconfigurable Datapath Array Architectures.- Transistor-Level Modeling.- Internal Power Dissipation Modeling and Minimization for Submicronic CMOS Design.- Impact of Voltage Scaling on Glitch Power Consumption.- Degradation Delay Model Extension to CMOS Gates.- Second Generation Delay Model for Submicron CMOS Process.- Asynchronous Circuit Design.- Semi-modular Latch Chains for Asynchronous Circuit Design.- Asynchronous First-in First-out Queues.- Comparative Study on Self-Checking Carry-Propagate Adders in Terms of Area, Power and Performance.- VLSI Implementation of a Low-Power High-Speed Self-Timed Adder.- Power Efficient Technologies.- Low Power Design Techniques for Contactless Chipcards.- Dynamic Memory Design for Low Data-Retention Power.- Double-Latch Clocking Scheme for Low-Power I.P. Cores.- Design of Multimedia Processing Applications.- Architecture, Design, and Verification of an 18 Million Transistor Digital Television and Media Processor Chip.- Cost-Efficient C-Level Design of an MPEG-4 Video Decoder.- Data-Reuse and Parallel Embedded Architectures for Low-Power, Real-Time Multimedia Applications.- AdiabaticDesign and ArithmeticModules.- Design of Reversible Logic Circuits by Means of Control Gates.- Modeling of Power Consumption of Adiabatic Gates versus Fan in and Comparison with Conventional Gates.- An Adiabatic Multiplier.- Logarithmic Number System for Low-Power Arithmetic.- Analog-Digital Circuits Modeling.- An Application of Self-Timed Circuits to the Reduction of Switching Noise in Analog-Digital Circuits.- PARCOURS — Substrate Crosstalk Analysis for Complex Mixed-Signal-Circuits.- Influence of Clocking Strategies on the Design of Low Switching-Noise Digital and Mixed-Signal VLSI Circuits.- Computer Aided Generation of Analytic Models for Nonlinear Function Blocks.

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