Interconnect Analysis and Synthesis / Edition 1

Interconnect Analysis and Synthesis / Edition 1

by Chung-Kuan Cheng, John Lillis, Shen Lin, Norman Chang
     
 

ISBN-10: 0471293660

ISBN-13: 9780471293668

Pub. Date: 11/03/1999

Publisher: Wiley

State-of-the-art methods and current perspectives on interconnect The irrepressible march toward smaller and faster integrated circuits has made interconnect a hot topic for semiconductor research. The effects of wire size, topology construction, and network design on system performance and reliability have all been thoroughly investigated in recent years.

Overview

State-of-the-art methods and current perspectives on interconnect The irrepressible march toward smaller and faster integrated circuits has made interconnect a hot topic for semiconductor research. The effects of wire size, topology construction, and network design on system performance and reliability have all been thoroughly investigated in recent years. Interconnect Analysis and Synthesis provides CAD researchers and engineers with powerful, state-of-the-art tools for the analysis, design, and optimization of interconnect. It brings together a wealth of information previously scattered throughout the literature, explaining in depth available analysis techniques and presenting a range of CAD algorithms for synthesizing and optimizing interconnect. Along with examples and results from the semiconductor industry and 150 illustrations, this practical work features:

• Models for interconnect as well as devices and the impact of scaling trends

• Modern analysis techniques, from matrix reduction and moment matching to transmission-line analysis

• An overview of the effects of inductance on on-chip interconnect

• Flexible CAD algorithms that can be generalized for different needs, from buffer insertion to wire sizing to routing topology

• Emphasis on realistic problem formulations, addressing key design tradeoffs such as those between area and performance

Product Details

ISBN-13:
9780471293668
Publisher:
Wiley
Publication date:
11/03/1999
Edition description:
New Edition
Pages:
262
Product dimensions:
6.34(w) x 9.67(h) x 0.80(d)

Table of Contents

Interconnect Models.

Device Models.

Interconnect Analysis.

Inductance and Inductive Coupling for On-chip Interconnect.

Synthesis: Overview and Static Topology Optimization.

Global Routing Topology Synthesis.

Optimization of Multi-Source Nets.

Timing Driven Maze Routing.

Customer Reviews

Average Review:

Write a Review

and post it to your social network

     

Most Helpful Customer Reviews

See all customer reviews >