Layout Minimization of CMOS Cells / Edition 1

Layout Minimization of CMOS Cells / Edition 1

by Robert L. Maziasz, John P. Hayes
     
 

ISBN-10: 0792391829

ISBN-13: 9780792391821

Pub. Date: 10/31/1991

Publisher: Springer US

Product Details

ISBN-13:
9780792391821
Publisher:
Springer US
Publication date:
10/31/1991
Series:
Springer International Series in Engineering and Computer Science, #160
Edition description:
1992
Pages:
169
Product dimensions:
9.21(w) x 6.14(h) x 0.50(d)

Related Subjects

Table of Contents

I. Introduction.- 1.1 Problem and Motivation.- 1.2 Layout Styles.- 1.2.1 Semi-Custom Layouts.- 1.2.2 Unstructured Methods.- 1.2.3 Programmable Logic Arrays.- 1.2.4 Gate Matrix Layouts.- 1.2.5 Functional Cells.- 1.3 Functional Cell Optimization.- 1.3.1 Layout Problem.- 1.3.2 Prior Work.- 1.4 Proposed Approach.- 1.4.1 Philosophy.- 1.4.2 Outline of the Book.- II. Functional Cell Layout Methods.- 2.1 Functional Cell Design.- 2.2 Survey of Prior Methods.- 2.2.1 Static Cells.- 2.2.2 Dynamic Cells.- 2.3 Critique of Prior Work.- III. Series-Parallel Cell Width Minimization.- 3.1 Graph Optimization Problems.- 3.2 Theory of Dual Trail Covering.- 3.3 Optimal Trail Covering without Reordering.- 3.4 Optimal Trail Covering with Reordering.- 3.5 Analysis of Complete Class of Practical Cells.- 3.6 Minimum-Width Rows of Cells.- IV. Planar Cell Width Minimization.- 4.1 Nonseries-Parallel Composition.- 4.1.1 Graph Composition.- 4.1.2 Trail Covering.- 4.2 P-TrailTrace Algorithm.- 4.2.1 Description.- 4.2.2 Design Example.- 4.2.3 Optimality.- 4.2.4 Time Complexity.- 4.3 Complete Study of Practical Planar Cells.- V. Single Cell Width and Height Minimization.- 5.1 Layout Problem.- 5.1.1 Constraints and Assumptions.- 5.1.2 Comparison to Other Assumptions.- 5.2 Extension of Series-Parallel Cell Theory.- 5.3 HR-TrailTrace Algorithm.- 5.3.1 Description.- 5.3.2 Design Example.- 5.3.3 Optimality.- 5.3.4 Time Complexity.- 5.4 Complete Study of Practical Cells.- 5.5 Planar Cell Layout.- VI. Cell Array Width and Height Minimization.- 6.1 Layout Problem.- 6.2 HRM-TrailTrace Algorithm.- 6.2.1 Description.- 6.2.2 Design Example.- 6.2.3 Optimality.- 6.2.4 Time Complexity.- 6.3 Experimental Results.- 6.3.1 Commercial Circuits.- 6.3.2 Published Layouts.- VII. Conclusions.- 7.1 Contributions.- 7.2 Practical Applications and Extensions.

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