Logic Design

by Wai-Kai Chen (Editor)

Overview

In this volume drawn from the VLSI Handbook, the focus is on logic design and compound semiconductor digital integrated circuit technology. Expert discussions cover topics ranging from the basics of logic expressions and switching theory to sophisticated

Product Details

ISBN-13:	9780203010150
Publisher:	CRC Press
Publication date:	03/19/2003
Sold by:	Barnes & Noble
Format:	eBook
Pages:	344
File size:	8 MB

About the Author

Wai-Kai Chen

Table of Contents

1	Expressions of Logic Functions
1.1	Introduction to Basic Logic Operations	1
1.2	Truth Tables	2
1.3	Karnaugh Maps	3
1.4	Binary Decision Diagrams	5
2	Basic Theory of Logic Functions
2.1	Basic Theorems	1
2.2	Implication Relations and Prime Implicants	4
	References	8
3	Simplification of Logic Expressions
3.1	Minimal Sums	1
3.2	Derivation of Minimal Sums by Karnaugh Map	2
3.3	Derivation of Minimal Sums for a Single Function by Other Means	6
3.4	Prime Implicates, Irredundant Conjunctive Forms, and Minimal Products	7
3.5	Derivation of Minimal Products by Karnaugh Map	10
	References	11
4	Binary Decision Diagrams
4.1	Basic Concepts	1
4.2	Construction of BDD Based on a Logic Expression	5
4.3	Data Structure	10
4.4	Ordering of Variables for Compact BDDs	10
4.5	Remarks	13
	References	13
5	Logic Synthesis with AND and OR Gates in Two Levels
5.1	Introduction	1
5.2	Design of Single-Output Minimal Networks with AND and OR Gates in Two Levels	2
5.3	Design of Multiple-Output Networks with AND and OR Gates in Two Levels	3
	References	9
6	Sequential Networks
6.1	Introduction	1
6.2	Flip-Flops and Latches	1
6.3	Sequential Networks in Fundamental Mode	3
6.4	Malfunctions of Asynchronous Sequential Networks	5
6.5	Different Tables for the Description of Transitions of Sequential Networks	7
6.6	Steps for the Synthesis of Sequential Networks	8
6.7	Synthesis of Sequential Networks	10
	References	19
7	Logic Synthesis with AND and OR Gates in Multi-levels
7.1	Logic Networks with AND and OR Gates in Multi-levels	1
7.2	General Division	2
7.3	Selection of Divisors	3
7.4	Limitation of Weak Division	5
	References	6
8	Logic Properties of Transitor Circuits
8.1	Basic Properties of Connecting Relays	1
8.2	Analysis of Relay-Contact Networks	3
8.3	Transistor Circuits	5
	References	12
9	Logic Synthesis with NAND (or NOR) Gates in Multi-levels
9.1	Logic Synthesis with NAND (or NOR) Gates	1
9.2	Design of NAND (or NOR) Networks in Double-Rail Input Logic by the Map-Factoring Method	2
9.3	Design of NAND (or NOR) Networks in Single-Rail Input Logic	5
9.4	Features of the Map-Factoring Method	8
9.5	Other Design Methods of Multi-Level Networks with a Minimum Number of Gates	9
	References	9
10	Logic Synthesis with a Minimum Number of Negative Gates
10.1	Logic Design of MOS Networks	1
10.2	Algorithm DIMN	5
	References	6
11	Logic Synthesizer with Optimizations in Two Phases
	References	7
12	Logic Synthesizer by the Transduction Method
12.1	Technology-Dependent Logic Optimization	1
12.2	Transduction Method for the Design of NOR Logic Networks	1
12.3	Various Transduction Methods	21
12.4	Design of Logic Networks with Negative Gates by the Transduction Method	23
	References	23
13	Emitter-Coupled Logic
13.1	Introduction	1
13.2	Standard ECL Logic Gates	1
13.3	Modification of Standard ECL Logic Gates with Wired Logic	6
13.4	ECL Series-Gating Circuits	7
	References	12
14	CMOS
14.1	CMOS (Complementary MOS)	1
14.2	Logic Design of CMOS Networks	3
14.3	Logic Design in Differential CMOS Logic	5
14.4	Layout of CMOS	6
14.5	Pseudo-nMOS	7
14.6	Dynamic CMOS	8
	References	10
15	Pass Transistors
15.1	Introduction	1
15.2	Electronic Problems of Pass Transistors	4
15.3	Top-Down Design of Logic Functions with Pass-Transistor Logic	6
	References	10
16	Adders
16.1	Introduction	1
16.2	Addition in the Binary Number System	1
16.3	Serial Adder	3
16.4	Ripple Carry Adder	4
16.5	Carry Skip Adder	6
16.6	Carry Look-Ahead Adder	8
16.7	Carry Select Adder	9
16.8	Carry Save Adder	11
	References	11
17	Multipliers
17.1	Introduction	1
17.2	Sequential Multiplier	1
17.3	Array Multiplier	3
17.4	Multiplier Based on Wallace Tree	4
17.5	Multiplier Based on a Redundant Binary Adder Tree	5
	References	7
18	Dividers
18.1	Introduction	1
18.2	Subtract-and-Shift Dividers	1
18.3	Higher Radix Subtract-and-Shift Dividers	5
18.4	Even Higher Radix Dividers with a Multiplier	8
18.5	Multiplicative Dividers	8
	References	8
19	Full-Custom and Semi-Custom Design
19.1	Introduction	1
19.2	Full-Custom Design Sequence of a Digital System	3
	References	5
20	Programmable Logic Devices
20.1	Introduction	1
20.2	PLAs and Variations	2
20.3	Logic Design with PLAs	5
20.4	Dynamic PLA	7
20.5	Advantages and Disadvantages of PLAs	7
20.6	Programmable Array Logic	9
	References	9
21	Gate Arrays
21.1	Mask-Programmable Gate Arrays	1
21.2	CMOS Gate Arrays	1
21.3	Advantages and Disadvantages of Gate Arrays	2
	References	5
22	Field-Programmable Gate Arrays
22.1	Introduction	1
22.2	Basic Structures of FPGAs	2
22.3	Various Field-Programmable Gate Arrays	3
22.4	Features of FPGAs	8
	References	9
23	Cell-Library Design Approach
23.1	Introduction	1
23.2	Polycell Design Approach	1
23.3	Hierarchical Design Approach	2
	References	3
24	Comparison of Different Design Approaches
24.1	Introduction	1
24.2	Design Approaches with Off-the-Shelf Packages	1
24.3	Full- and Semi-Custom Design Approaches	2
24.4	Comparison of All Different Design Approaches	4
	References	4
25	Materials
25.1	Introduction	1
25.2	Compound Semiconductor Materials	1
25.3	Why III-V Semiconductors?	2
25.4	Heterojunctions	3
	References	5
26	Compound Semiconductor Devices for Digital Circuits
26.1	Introduction	1
26.2	Unifying Principle for Active Devices: Charge Control Principle	1
26.3	Comparing Unipolar and Bipolar Transistors	7
26.4	Typical Device Structures	14
	References	17
27	Logic Design Principles and Examples
27.1	Introduction	1
27.2	Static Logic Design	1
27.3	Transient Analysis and Design for Very-High-Speed Logic	8
	References	17
28	Logic Design Examples
28.1	Design of MESFET and HEMT Logic Circuits	1
28.2	HBT Logic Design Examples	10
	References	24
	Index	1