Logic Synthesis for Low Power VLSI Designs

Overview

Logic Synthesis for Low Power VLSI Designs presents a systematic and comprehensive treatment of power modeling and optimization at the logic level. More precisely, this book provides a detailed presentation of methodologies, algorithms and CAD tools for power modeling, estimation and analysis, synthesis and optimization at the logic level. Logic Synthesis for Low Power VLSI Designs contains detailed descriptions of technology-dependent logic transformations and optimizations, technology decomposition and mapping,...

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Paperback (Softcover reprint of the original 1st ed. 1998)
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Overview

Logic Synthesis for Low Power VLSI Designs presents a systematic and comprehensive treatment of power modeling and optimization at the logic level. More precisely, this book provides a detailed presentation of methodologies, algorithms and CAD tools for power modeling, estimation and analysis, synthesis and optimization at the logic level. Logic Synthesis for Low Power VLSI Designs contains detailed descriptions of technology-dependent logic transformations and optimizations, technology decomposition and mapping, and post-mapping structural optimization techniques for low power. It also emphasizes the trade-off techniques for two-level and multi-level logic circuits that involve power dissipation and circuit speed, in the hope that the readers can better understand the issues and ways of achieving their power dissipation goal while meeting the timing constraints.
Logic Synthesis for Low Power VLSI Designs is written for VLSI design engineers, CAD professionals, and students who have had a basic knowledge of CMOS digital design and logic synthesis.

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Editorial Reviews

Booknews
Provides a detailed presentation of methodologies, algorithms, and CAD tools for power modeling, estimation and analysis, synthesis and optimization at the logic level. Topics include two-level logic minimization in PLAs, technology dependent optimization for low power, and the power optimization and synthesis environment (POSE). Intended for VLSI design engineers, CAD professionals, and students who have a basic knowledge of CMOS digital design and logic synthesis. Annotation c. by Book News, Inc., Portland, Or.
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Product Details

  • ISBN-13: 9781461374909
  • Publisher: Springer US
  • Publication date: 10/28/2012
  • Edition description: Softcover reprint of the original 1st ed. 1998
  • Edition number: 1
  • Pages: 236
  • Product dimensions: 6.14 (w) x 9.21 (h) x 0.54 (d)

Table of Contents

Preface. I: Background, Terminology, and Power Modeling. 1. Introduction. 2. Technology Independent Power Analysis and Modeling. II: Two-Level Function Optimization for Low Power. 3. Two-Level Logic Minimization in CMOS Circuits. 4. Two-Level Logic Minimization in PLAs. III: Multi-Level Network Optimization for Low Power. 5. Logic Restructuring for Low Power. 6. Logic Minimization for Low Power. 7. Technology Dependent Optimization for Low Power; Chi-ying Tsui. 8. Post Mapping Structural Optimization for Low Power. IV: Power Optimization Methodology. 9. POSE: Power Optimization and Synthesis Environment: (http://atrak.usc.edu/~pose) V: Conclusion. 10. Concluding Remarks. Index.

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