Long-Term Reliability of Nanometer VLSI Systems: Modeling, Analysis and Optimization

by Sheldon Tan, Mehdi Tahoori, Taeyoung Kim, Shengcheng Wang, Zeyu Sun

Overview

This book provides readers with a detailed reference regarding two of the most important long-term reliability and aging effects on nanometer integrated systems, electromigrations (EM) for interconnect and biased temperature instability (BTI) for CMOS devices.  The authors discuss in detail recent developments in the modeling, analysis and optimization of the reliability effects from EM and BTI induced failures at the circuit, architecture and system levels of abstraction.  Readers will benefit from a focus on topics such as recently developed, physics-based EM modeling, EM modeling for multi-segment wires, new EM-aware power grid analysis, and system level EM-induced reliability optimization and management techniques.

• Reviews classic Electromigration (EM) models, as well as existing EM failure models and discusses the limitations of those models;
• Introduces a dynamic EM model to address transient stress evolution, in which wires are stressed under time-varying current flows, and the EM recovery effects. Also includes new, parameterized equivalent DC current based EM models to address the recovery and transient effects;
• Presents a cross-layer approach to transistor aging modeling, analysis and mitigation, spanning multiple abstraction levels;
• Equips readers for EM-induced dynamic reliability management and energy or lifetime optimization techniques, for many-core dark silicon microprocessors, embedded systems, lower power many-core processors and datacenters.

Product Details

ISBN-13:	9783030261726
Publisher:	Springer-Verlag New York, LLC
Publication date:	09/12/2019
Sold by:	Barnes & Noble
Format:	eBook
File size:	67 MB
Note:	This product may take a few minutes to download.

About the Author

Sheldon Tan is a Professor in the Department of Electrical and Computer Engineering, University of California, Riverside, CA. He also is a cooperative faculty member in the   Department of Computer Science and Engineering at UCR. He  received Ph.D. degree in electrical and computer engineering from the University of Iowa, Iowa City, in 1999. His research interests include VLSI reliability modeling, optimization and management at circuit and system levels, hardware security, thermal modeling, optimization and dynamic thermal management for many-core processors, parallel computing and adiabatic and Ising computing based on GPU and multicore systems. He has published more 290 technical papers and has co-authored 6 books on those areas. Dr. Tan received NSF CAREER Award in 2004. He also received three Best Paper Awards from ASICON’17, ICCD'07, DAC’09. He also received the Honorable Mention Best Paper Award from SMACD’18.  He was a Visiting Professorof Kyoto University as a JSPS Fellow from Dec. 2017 to Jan. 2018. He is now serving as Editor in Chief for Elsevier’s Integration, the VLSI Journal, the Associate Editor for three journals: IEEE Transaction on VLSI Systems (TVLSI), ACM Transaction on Design Automation of Electronic Systems (TODAE) and Elsevier’s Microelectronics Reliability.

Mehdi Tahoori is a full professor and Chair of Dependable Nano-Computing (CDNC) at the Institute of Computer Science&Engineering (ITEC), Department of Computer Science, Karlsruhe Institute of Technology (KIT), Germany. He received his PhD and M.S. degrees in Electrical Engineering from Stanford University in 2003 and 2002, respectively, and a B.S. in Computer Engineering from Sharif University of Technology in Iran, in 2000. In 2003, he joined the Electrical and Computer Engineering Department at the Northeastern University as an assistant professor where he promoted to the rank of associate professor with tenure in 2009. From August to December 2015, he was a visiting professor at VLSI Design and Education Center (VDEC), University of Tokyo, Japan. From 2002 to 2003, he was a Research Scientist with Fujitsu Laboratories of America, Sunnyvale, CA, in the area of advanced computer-aided research, engaged in reliability issues in deep-submicrometer mixed-signal very large-scale integration (VLSI) designs. He holds several pending and granted U.S. and international patents. He has authored over 250 publications in major journals and conference proceedings on a wide range of topics, from dependable computing and emerging nanotechnologies to system biology. His current research interests include nanocomputing, reliable computing, VLSI testing, reconfigurable computing, emerging nanotechnologies, and systems biology. Prof. Tahoori was a recipient of the National Science Foundation Early Faculty Development (CAREER) Award. He has been a program committee member, organizing committee member, track and topic chair, as well as workshop, panel, and special session organizer of various conferences and symposia in the areas of VLSI design automation, testing, reliability, and emerging nanotechnologies, such as ITC, VTS, DAC, ICCAD, DATE, ETS, ICCD, ASP-DAC, GLSVLSI, and VLSI Design. He is currently an associate editor for IEEE Design and Test Magazine (D&T), coordinating editor for Springer Journal of Electronic Testing (JETTA), associate editor of VLSI Integration Journal, and associate editor of IET Computers and Digital Techniques.

He was an associate editor of ACM Journal of Emerging Technologies for Computing. He received a number of best paper nominations and awards at various conferences and journals, including ICCAD 2015 and TODAES 2017. He is the Chair of the ACM SIGDA Technical Committee on Test and Reliability.

                

Taeyoung Kim has received his B.S. degree in electronics engineering from Konkuk University,Seoul, Korea in 2005, the M.S. degree in electrical engineering from University of Virginia, Charlottesville, VA, USA in 2012, and the Ph.D. degree in computer science from University of California, Riverside, CA, USA in 2017. He is currently a senior-level software engineer at Intel Corporation, in Hillsboro, Oregon. Also, he is currently an associate editor for Integration, the VLSI Journal. 

 

Shengcheng Wang has received his B.S. degree in microelectronics from Nankai University, Tianjin, China in 2007, the M.S. degree in microelectronics from Peking University, Beijing, China in 2010, and the Ph.D. degree in computer science from Karlsruhe Institute of Technology, Karlsruhe, Germany in 2018. He is currently a research scientist at Agency for Science, Technology and Research (A*STAR) Institute of Microelectronics (IME), Singapore.

 

Zeyu Sun has received his B.S. degree in Electronic and Computer Engineering at Hong Kong University of Science and Technology (HKUST) in 2015. He is currently a Ph.D. student in the Department of Electrical and Computer Engineering at the University of California, Riverside.  

 

Table of Contents

Part I. New physics-based EM analysis and system-level dynamic reliability management.- Chapter 1. Introduction.- Chapter 2. Physics Based EM Modeling.- Chapter 3. Fast EM Stress Evolution Analysis Using Krylov Subspace Method.- Chapter 4. Fast EM Immortatlity Analysis For Multisegment Copper Interconnect Wires.- Chapter 5. Dynamic EM Models For Transient Stress Evolution and Recovery.- Chapter 6. Compact EM Models for Multi-SEgment Interconnect Wires.- Chapter 7. EM Assesment for Power Grid Networks.- Chapter 8. Resource Based EM Modeling for Multi-Crore Microprocessors.- Chapter 9. DRM and Optimization for Real Time Embedded Systems.- Chapter 10. Learning Based DRM and Energy Optimization for Many Core Dark Silicaon Processors.- Chapter 11. Recovery Aware DRM for Near Threshold Dark Silicon Processors.- Chapter 12. Cross-Layer DRM and Optimization For Datacenter Systems.- Part II. Transistor Aging Effects and Reliability.- 13. Introduction.- Chapter 14. Aging AWare Timings Analysis.- Chapter 15. Aging Aware Standard Cell Library Optimization Methods.- Chapter 16. Aging Effects In Sequential Elements.- Chapter 17. Aging Guardband Reduction Through Selective Flip Flop Optimization.- Chapter 18. Workload Aware Static Aging Monitoring and Mitigation of Timing Critical Flip Flops.- Chapter 19. Aging Relaxation at Micro Architecture Level Using Special NOPS.- Chapter 20. Extratime Modelling and Analyis of Transistor Agin at Microarchitecture Level.- Chapter 21. Reducing Processor Wearout By Exploiting The Timing Slack of Instructions.