Low Power Design with High-Level Power Estimation and Power-Aware Synthesis

by Sumit Ahuja, Avinash Lakshminarayana, Sandeep Kumar Shukla

Overview

This book presents novel research techniques, algorithms, methodologies and experimental results for high level power estimation and power aware high-level synthesis. Readers will learn to apply such techniques to enable design flows resulting in shorter time to market and successful low power ASIC/FPGA design.

Product Details

ISBN-13:	9781461408710
Publisher:	Springer New York
Publication date:	10/21/2011
Edition description:	2012
Pages:	170
Product dimensions:	6.10(w) x 9.25(h) x 0.02(d)

Table of Contents

Introduction.- Related Work.- Background.- Architectural Selection using High Level Synthesis.- Statistical Regression Based Power Models.- Coprocessor Design Space Exploration Using High Level Synthesis.- Regression-based Dynamic Power Estimation for FPGAs.- High Level Simulation Directed RTL Power Estimation.- Applying Verification Collaterals for Accurate Power Estimation.- Power Reduction using High-Level Clock-gating.- Model-Checking to exploit Sequential Clock-gating.- System Level Simulation Guided Approach for Clock-gating.- Conclusions.