Table of Contents
1 Introduction to Low Power Issues in VLSI 1
1.1 Introduction to VLSI 1
1.2 Low Power IC Design beyond Sub-20 nm Technology 2
1.3 Issues Related to Silicon Manufacturability and Variation 3
1.4 Issues Related to Design Productivity 4
1.5 Limitation Faced by CMOS 4
1.6 International Technology Roadmap for Semiconductors 5
1.7 Different Groups of MOSFETs 8
1.8 Three MOS Types 9
1.9 Low Leakage MOSFET 9
1.10 Importance of Subthreshold Slope 10
1.11 Why Is Subthreshold Current Exponential in Nature? 13
1.12 Subthreshold Leakage and Voltage Limits 15
1.13 Importance of Subthreshold Slope in Low Power Operation 16
1.14 Ultralow Voltage Operation 16
1.15 Low Power Analog Circuit Design 17
1.16 Fundamental Consequence of Lowering Supply Voltage 18
1.17 Analog MOS Transistor Performance Parameters 19
Summary 21
References 22
2 Scaling and Short Channel Effects in MOSFET 24
2.1 MOSFET Scaling 24
2.2 International Technology Roadmap for Semiconductors 24
2.3 Gate Oxide Scaling 25
2.4 Gate Leakage Current 25
2.5 Mobility 26
2.6 High-k Gate Dielectrics 26
2.7 Key Guidelines for Selecting an Alternative Gate Dielectric 26
2.8 Materials 26
2.9 Gate Tunneling Current 27
2.10 Gate Length Scaling 27
2.11 Introduction to Short Channel Effect in MOSFET 27
2.11.1 Reduction of Effective Threshold Voltage 28
2.11.2 Drain-induced Barrier Lowering 28
2.11.3 Mobility Degradation and Surface Scattering 30
2.11.4 Surface Scattering 32
2.11.5 Hot Carrier Effect 32
2.11.6 Punch-through Effect 32
2.11.7 Velocity Saturation Effect 32
2.11.8 Increase in Off-state Leakage Current 34
2.12 Motivation for Present Research 34
2.12.1 Lightly Doped Drain Structure 35
2.12.2 Channel Engineering Technique 36
2.12.3 Gate Engineering Technique 37
2.12.4 Single Halo Dual Material Gate MOSFET 37
2.12.5 Double Halo Dual Material Gate MOSFET 38
2.12.6 Double Gate MOSFET 38
2.12.7 Dual Material Double Gate MOSFET 40
2.12.8 Triple Material Double Gate MOSFET 41
2.12.9 FinFET 41
2.12.10 Triple Gate MOSFET 43
2.12.11 Gate-all-around MOSFET 43
2.12.12 Surrounding Gate MOSFET 43
2.12.13 Silicon Nanowires 44
2.13 Fringing-induced Barrier Lowering 45
2.14 Silicon-on-insulator MOSFETs 45
2.15 Nonconventional Double Gate MOSFETs 46
2.16 Tunnel Field-effect Transistor 63
2.17 IMOS Device 65
2.18 Summary 65
References 66
3 Advanced Energy-reduced CMOS Inverter Design 71
3.1 Introduction 71
3.1.1 Transfer Characteristics of Inverter 71
3.1.2 Static CMOS Inverter in Super-threshold Regime 73
3.1.3 Introduction to Sub-threshold Logic 94
3.1.4 Summary 107
References 108
4 Advanced Combinational Circuit Design 112
Introduction 112
4.1 Static CMOS Logic Gate Design 112
4.2 Complementary Properties of CMOS Logic 112
4.2.1 CMOS NAND Gate 113
4.2.2 CMOS NOR Gate 113
4.2.3 Some More Examples of CMOS Logic 115
4.2.4 XOR or Nonequivalence Gate Using CMOS Logic 116
4.2.5 XOR-XNOR or Equivalence Gate Using CMOS Logic 116
4.2.6 And-Or-Invert and Or-And-Invert Gates 117
4.2.7 Full Adder Circuits Using CMOS Logic 118
4.3 Pseudo-nMOS Gates 120
4.3.1 Why the Name Is Pseudo-nMOS? 123
4.3.2 Ratioed Logic 123
4.3.3 Operation of Pseudo-nMOS Inverter 124
4.4 Pass-transistor Logic 125
4.5 Complementary Pass Transistor Logic 127
4.6 Signal Restoring Pass Transistor Logic Design 128
4.7 Sizing of Transistor in CMOS Design Style 129
4.8 Introduction to Logical Effort 132
4.8.1 Definitions of Logical Effort 132
4.9 Delay Estimation by Logical Effort 135
4.10 Introduction to Transmission Gate 136
4.10.1 Use of CMOS TG as Switch 138
4.10.2 2:1 Multiplexer Using TG 141
4.10.3 XOR Gate Using TG -141
4.10.4 XNOR Gate Using TG 143
4.10.5 Transmission Gate Adders 144
4.10.6 More Examples of TG Logic 144
4.11 Tristate Buffer 145
4.12 Transmission Gates and Tristates 146
4.13 Implementation of Combinational Circuit Using DTMOS Logic for Ultra low Power Application 149
4.14 ECLR Structure 154
4.14.1 Power Consumption 175
4.14.2 Propagation Delay 175
References 175
5 Advanced Energy-reduced Sequential Circuit Design 177
5.1 Introduction to Sequential Circuit 177
5.2 Basics of Regenerative Circuits 177
5.3 Basic SR Flip-Hop/Latch 181
5.3.1 NAND Gate-based Negative Logic SR Latch 183
5.3.2 Clocked SR Latch 183
5.4 Clocked JK Latch 185
5.4.1 Toggle Switch 186
5.5 Master-slave Flip-flop 186
5.6 D Latch 187
5.6.1 Positive and Negative Latch 188
5.6.2 Multiplexer-based Latch 188
5.7 Master-slave Edge-triggered Flip-flops 190
5.8 Timing Parameters for Sequential Circuits 192
5.8.1 Timing of Multiplexer-based Master-slave Flip- flop 194
5.8.2 The Sizing Requirements for the Transmission Gates 195
5.9 Clock Skews due to Nonideal Clock Signal 196
5.10 Design and Analysis of the Flip-flops Using DTMOS Style 197
5.10.1 SR Latch and Flip-flop 197
5.10.2 JK Latch and JK Flip-flop 201
5.10.3 D Flip-flop 202
5.11 Adiabatic Flip-flop 205
References 207
6 Introduction to Memory Design 208
Introduction 208
6.1 Types of Semiconductor Memory 208
6.2 Memory Organization 210
6.3 Introduction to DRAM 212
6.4 One-transistor DRAM Cell 213
6.4.1 Write 214
6.4.2 Hold 214
6.4.3 Read 215
6.5 Capacitor in DRAM 217
6.6 Refresh Operation of DRAM 219
6.7 DRAM Types 220
6.7.1 FPM DRAMS 220
6.7.2 Extended Data Out DRAMs 221
6.7.3 Burst EDO DRAMs 221
6.7.4 ARAM 221
6.7.5 Cache DRAM 221
6.7.6 Enhanced DRAM (EDRAM) 221
6.7.7 Synchronous DRAM 222
6.7.8 Double Data Read DRAMs 222
6.7.9 Synchronous Graphic RAM 222
6.7.10 Enhanced Synchronous DRAMs 222
6.7.11 Video DRAMs 223
6.7.12 Window DRAMs 223
6.7.13 Pseudo-static RAMs 223
6.7.14 Rambus DRAMs 223
6.7.15 Multibank DRAM 224
6.7.16 Ferroelectric DRAM 224
6.8 SOI DRAM 225
6.8.1 Operating Principle 225
6.8.2 Design Considerations of SOI DRAM 226
6.9 Introduction to SRAM 226
6.10 SRAM Cell and Its Operation 227
6.11 SRAM Cell Failures 228
6.12 Performance Metrics of SRAM 228
6.12.1 Static Noise Margin 228
6.12.2 Reliability Issues of 6-T SRAM 229
6.13 Read-only Memory 230
6.14 EPROM 233
6.15 Electrically Erasable Programmable Read-only Memory (E2PROM) 234
6.16 Flash Memory 236
6.17 Summary 238
References 239
7 Analog Low Power VLSI Circuit Design 242
7.1 Analog Low Power Design: Problems with Transistor Mismatch 242
7.2 Mixed-signal Design with Sub-100 nm Technology 243
7.3 Challenges in MS Design in Sub-100 nm Space 244
7.3.1 Lack of Convergence of Technology 244
7.3.2 Digital Scaling 245
7.3.3 Memory Scaling 246
7.3.4 Analog Scaling 247
7.3.5 Degraded SNR 247
7.3.6 Degradation in Intrinsic Gain 248
7.3.7 Device Leakage 248
7.3.8 Mismatch due to Reduced Matching 248
7.3.9 Availability of Models 248
7.3.10 Passives 248
7.3.11 RF Scaling 249
7.3.12 Issues Related with Power Devices 250
7.4 Basics of Switched-capacitor Circuits 250
7.4.1 Resistor Emulation Using SC Network 251
7.4.2 Integrator Using SC Circuits 252
7.4.3 SC Integrator Sensitive to Parasitic 255
7.4.4 Low Power Switched-capacitor Circuit 256
7.5 Current Source/Sink 258
7.5.1 Technique to Increase Output Resistance 261
7.6 Low Power Current Mirror 263
7.6.1 Use of Current Mirrors in IC 263
7.6.2 Simple Current Mirror 265
7.6.3 Wilson Current Mirror 267
7.6.4 Cascode Current Mirror 268
7.6.5 Low Voltage Current Mirror 270
7.7 Fundamentals of Current/Voltage Reference 273
7.7.1 Another Way to Obtain Simple Bootstrap Voltage Reference Circuit with Start-up Circuit 279
7.8 Bandgap Voltage Reference 282
7.8.1 Positive TC Voltage 282
7.8.2 Negative TC Voltage 283
7.9 An Introduction to Analog Design Automation 284
7.9.1 Survey of Previous Analog Design Flow 285
7.9.2 Analog and Mixed-signal Design Process 288
7.9.3 Hierarchical Analog Design Methodology 290
7.9.4 Current Status for the Main Tasks in Analog Design Automation 292
7.10 Field-programmable Analog Arrays 299
7.11 Summary 301
References 301
Index 305
