Microscale Heat Conduction in Integrated Circuits and Their Constituent Films / Edition 1

by Y. Sungtaek Ju, Kenneth E. Goodson

Overview

The study of thermal phenomena in microdevices has attracted significant attention recently. The interdisciplinary nature of this topic, however, makes it very difficult for researchers to fully understand details of research results presented in journal articles. For many researchers intending to be active in this field, therefore, a more comprehensive treatment, complete with sufficient background information, is urgently needed.

Advances in semiconductor device technology render the thermal characterization and design of ICs increasingly more important. The present book discusses experimental and theoretical studies of heat transfer in transistors and interconnects. A novel optical thermometry technique captures temperature fields with high temporal and spatial failures in devices that are subjected to electrical overstress (EOS) and electrostatic discharge (ESD). Also reported are techniques for determining the thermal transport properties of dielectric passivation layers and ultra-thin silicon-on-insulator (SOI) layers. Theoretical analysis on the data yields insight into the dependence of thermal properties on film processing conditions. The techniques and data presented here will greatly aid the thermal engineering of interconnects and transistors.

Product Details

ISBN-13:	9780792385912
Publisher:	Springer US
Publication date:	08/31/1999
Series:	Microsystems , #6
Edition description:	1999
Pages:	102
Product dimensions:	6.10(w) x 9.25(h) x 0.01(d)

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Chapter 1Introduction

1.1 Thermal Issues in Integrated Circuit Elements

1.1.1 Current Trends in IC Technology

Miniaturization of circuit elements has played an essential role in improving the performance, capacity, and functionality of semiconductor integrated circuits. Transistors with shorter channel lengths can switch faster. The capability to integrate a larger number of devices generally translates into enhanced capacity and functionality. For these reasons, the semiconductor industry is expected to continue its miniaturization efforts in the coming decades. Indeed, minimum feature sizes of integrated circuit components are projected to reach the sub-0.1 um regime during the first decade of the 21 st century. A recent study (Timp et al., 1997) demonstrated the operation of field-effect transistors with 61 nn gate width.

Reducing lateral dimensions of transistors and interconnects, however, is only one aspect of semiconductor technology development. To meet future demands on integrated circuits, progress in other areas, such as introduction of new device structures and materials with superior properties, is also necessary. One example is devices built on silicon-on-insulator (SOI) substrates, which consist of thin silicon device layers and buried insulating layers. Schematic diagrams of the cross section of an SOI field-effect transistor and a related double-gate structure are shown in Fig. 1.1. SOI devices offer significant performance advantages over circuits fabricated from conventional bulk silicon substrates (Colinge, 1991). The advantages at the device level include reduced values of the threshold voltage, the leakage current, and the junction capacitance, which are promising for high-frequency, low-power circuits. For high-power circuits, SOI technology is interesting because the buried oxide can increase the breakdown voltage of devices and can facilitate the integration of multiple devices onto a single chip. In addition to new types of devices, recent research has focused on new passivation materials with low dielectric constants, generally referred to as low-k dielectrics. This has been motivated by the need to diminish interconnect RC delay, which recently has begun to account for a large fraction of overall circuit delay in advanced logic circuits. The interconnect delay can more than offset the performance gain achieved by reducing channel lengths and/or by using SOI substrates.

While these advancements offer tremendous benefits in electrical performance of integrated circuits, they raise several thermal issues that must be properly addressed to take full advantage of potential improvement and to ensure reliable operation. The following sections discuss these thermal problems and challenges they pose to the analysis and characterization of IC elements.

1.1.2 Challenges Associated with Miniaturization

Since the mobility of charge carriers is a function of temperature, a knowledge of the temperature field in a device is a prerequisite for accurate predictions of the behavior of the device under various operating and stressing conditions. For this reason existing simulation tools solve the heat diffusion equation together with equations describing charge carrier concentration and energy distributions. As semiconductor devices continue to shrink, however, the validity of the heat diffusion equation needs to be carefully scrutinized. Continuum description of heat transport is no longer valid when characteristic system dimensions are comparable to or smaller than the heat carrier mean free path. The non-local non-equilibrium nature of heat transport causes the spatial temperature and heat flux distributions to deviate considerably from the predictions of the diffusion equation (Mahan and Claro, 1988; Chen, 1997a).

To illustrate this idea more quantitatively, the temperature rise of a spherical heat source embedded in an infinite medium is calculated using both the diffusion equation and the Boltzmann transport equation (BTE). The situation approximates that in a field-effect transistor, where heat generation is highly localized to a region near the drain junction. For simplicity, heat carriers are assumed to have an energy-independent mean free path, which is the average distance traveled by the heat carriers between successive scattering events. The temperature of the medium at infinity is maintained at To. In the limit where the mean free path is negligible compared with the heat source radius, the solution of the Boltzmann equation coincides with that of the diffusion equation. The two solutions deviate from each other when the mean free path is comparable to or larger than the heat source radius. Figure 1.2 plots the ratio between the calculated temperature differences, which grows approximately linearly with the mean free path.

One major challenge in the microscopic analysis of energy transport lies in accurate determination of the heat carrier mean free path. In crystalline semiconductors heat is transported predominantly by phonons, which are energy quanta of lattice vibrations (Fulkerson et al., 1968). Direct measurements of the phonon mean free path have been difficult due to the inadequate energy resolution of phonon spectroscopy using X-ray or neutron beams. The only practical way to estimate the phonon mean free paths has been to use semi-phenomenological models for the thermal conductivity of semiconductors. A number of models have been developed which reproduce the experimental data of bulk semiconductors reasonably well. But it is unclear whether this agreement can be interpreted as a definite proof of the validity of a particular model. The nonuniqueness of adjustable model parameters, for instance, led to contradictory conclusions regarding the role of high-frequency phonons in heat conduction (Sood and Roy, 1993).

1.1.3 Challenges Associated with SOI Devices

The size effect on the thermal conductivity of thin silicon films is also expected to affect the thermal conduction cooling of SOI devices. Lateral heat conduction in the device layer, which is typically less than 100 nm thick, is impeded by phononboundary scattering. A similar problem exists for a double gate structure illustrated in Fig. 1.1. Reduced lateral heat conduction, combined with the presence of a buried amorphous silicon-dioxide layer, significantly impairs vertical and lateral cooling of active regions and causes the peak temperature rises in SOI devices to be much higher than that in comparable bulk devices. The impact of the higher temperatures on device behavior and on device and metallization reliability needs to be carefully considered as part of the circuit design process.

Low-power circuits make use of exceptionally short and thin channel regions, which increase the peak junction temperature by diminishing its thermal capacitance and by strongly reducing the ability of the silicon to laterally conduct heat away from active regions. The strong temporal dependence of the thermal impedance causes model parameters extracted using steady-state measurements to be inappropriate for transient circuit simulations. Temperature-dependent device model parameters such as the low-field mobility and the saturation velocity can only be extracted through careful consideration of the temperature fields that prevail in devices during electrical characterization. Figure 1.3 shows the results of transient measurements of the current-voltage characteristics of SOI MOSFETs, which were obtained by applying electrical pulses to the drain (Yasuda et al., 1991). At short times after the pulse initiation, the temperature rise was smaller, and the drain current was found to be higher than that corresponding to steady-state operation. One exception is at small drain biases, where the temperature rise is small due to the lower amount of heat generation even at steady state. Figure 1.3 shows that self-heating causes the drain conductance to vary by more than 15 percent for large drain voltages depending on the timescale of the electrical stress.

The motivation for studying SOI temperature fields is particularly strong in connection with the reliability engineering of devices that must withstand large electrical stresses during short timescales. The rapid temperature rise during brief electrical overstress is known to be responsible for failures of transistors (Amerasekera and Duvvury, 1995). For heating events with duration less than a few microseconds, such as in electrostatic discharge (ESD), thermal conduction is confined within a few micrometers of active regions, within which the buried oxide exerts a particularly large impact on thermal conduction cooling. Figure 1.4 plots the failure voltages of SOI transistors subjected to human-body-model (HBM) electrical stresses (Chan, 1995). The HBM emulates the discharge process resulting from physical contact of a chip with a human body. The failure voltage increases with device layer thickness, which reflects the significance of heat conduction along silicon device layers on device temperature rises. The prediction shown in Fig. 1.4 corresponds to the bias voltage that results in a threshold peak temperature (Amerasekera and Duvvury, 1995) as predicted by solving the heat diffusion equation. Brief transient heating can also be very important for SOI power devices. The resulting temperature increase can augment thermal instability among multi-finger bipolar devices, reduce the electrical conductance of field-effect transistors, and reduce the lifetime of devices and metallization.

The analysis and design of SOI devices require accurate property data for constituent materials and thermometry to verify predictions. No experimental data exist for the thermal conductivity of silicon films with thickness of practical importance. Existing thermometry techniques can provide only spatially averaged temperature fields, which are inappropriate especially for SOI power transistors with considerable temperature nonhomogeneity...

Table of Contents

1 Introduction.- 1.1 Thermal Issues in Integrated Circuit Elements.- 1.2 Scope of Research.- 1.3 Book Overview.- 2 Review of Microscale Thermometry Techniques.- 2.1 Electrical Methods.- 2.2 Optical Methods.- 3 High Spatial and Temporal Resolution Thermometry.- 3.1 Thermoreflectance Thermometry Technique.- 3.2 Thermal Characterization of Silicon-on-Insulator High-Voltage Transistors.- 3.3 Thermal Characterization of Interconnects.- 4 Thermal Properties of Amorphous Dielectric Films.- 4.1 Thermal Characterization Techniques for Dielectric Films.- 4.2 Heat Transport in Amorphous Silicon Dioxide.- 5 Heat Conduction in Crystalline Silicon Films.- 5.1 Phonon Dispersion and its Implication on the Estimation of the Phonon Mean Free Path.- 5.2 Measurements of In-Plane Thermal Conductivities of Silicon Films.- 5.3 Heat Conduction in Semiconductors at High Temperatures.- 5.4 Prediction of the In-Plane Thermal Conductivity of Silicon Thin Films.- 5.5 Simplified Phonon Transport Equations Accounting for Phonon Dispersion.- 5.6 Hot Phonon Effects.- 6 Summary and Recommendations.- 6.1 Atomistic Simulations of Heat Transport.- 6.2 Thermal Conductivities of Nanostructures.- 6.3 Detailed Simulations of Semiconductor Device.- A Uncertainty Analysis.- A.1 Uncertainly in the Temperature Rise.- A.2 Uncertainly in the Thermal Properties of Dielectric Films.- A.3 Uncertainly in the In-Plane Thermal Conductivity of Thin Films.