Mobile 3D Graphics SoC: From Algorithm to Chip

by Hoi-Jun Yoo, Jeong-Ho Woo, Ju-Ho Sohn, Byeong-Gyu Nam

Overview

The first book to explain the principals behind mobile 3D hardware implementation, helping readers understand advanced algorithms, produce low-cost, low-power SoCs, or become familiar with embedded systems

As mobile broadcasting and entertainment applications evolve, there is increasing interest in 3D graphics within the field of mobile electronics, particularly for handheld devices. In Mobile 3D Graphics SoC, Yoo provides a comprehensive understanding of the algorithms of mobile 3D graphics and their real chip implementation methods. 3D graphics SoC (System on a Chip) architecture and its interaction with embedded system software are explained with numerous examples. Yoo divides the book into three sections: general methodology of low power SoC, design of low power 3D graphics SoC, and silicon implementation of 3D graphics SoCs and their application to mobile electronics. Full examples are presented at various levels such as system level design and circuit level optimization along with design technology. Yoo incorporates many real chip examples, including many commercial 3D graphics chips, and provides cross-comparisons of various architectures and their performance. Furthermore, while advanced 3D graphics techniques are well understood and supported by industry standards, this is less true in the emerging mobile applications and games market. This book redresses this imbalance, providing an in-depth look at the new OpenGL ES (The Standard for Embedded Accelerated 3D Graphics), and shows what these new embedded systems graphics libraries can provide for 3D graphics and games developers.

Product Details

ISBN-13:	9780470823774
Publisher:	Wiley
Publication date:	03/01/2010
Series:	IEEE Press
Pages:	352
Product dimensions:	6.80(w) x 9.90(h) x 0.90(d)

About the Author

Hoi Jun Yoo is a Professor of Electrical Engineering at the Korea Advanced Institute of Science and Technology (KAIST) and currently serves as Project Manager for the Korea Ministry of Information and Communication's IT SoC and Post-PC programs. Yoo's industry experience includes time with Bell Communications Research in Red Bank, NJ, where he invented the two-dimensional phase-locked VCSEL array, the front-surface-emitting laser, and the high-speed lateral HBT, as well as an appointment as Manager of a DRAM design group at Hyundai Electronics. He has written popular Korean books on DRAM design and high performance DRAM, and in 1994 received the Electronic Industrial Association of Korea Award for his contribution to DRAM technology, along with the Korea Semiconductor Industry Association Award in 2002. Yoo is the founder the System Integration and IP Authoring Research Center (SIPAC), a national-level center funded by the Korean government. Yoo holds a B.S. in Electronic Engineering from Seoul National University and an M.S. and Ph.D degrees in Electrical Engineering from KAIST.

Jeong-Ho Woo is a PhD candidate at KAIST. Ju-Ho Sohn works at LG Electronics, and Byung-Gyu Nam works for Samsung.

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Table of Contents

Preface ix

1 Introduction 1

1.1 Mobile 3D Graphics 1

1.2 Mobile Devices and Design Challenges 3

1.2.1 Mobile Computing Power 3

1.2.2 Mobile Display Devices 5

1.2.3 Design Challenges 5

1.3 Introduction to SoC Design 6

1.4 About this Book 7

2 Application Platform 9

2.1 SoC Design Paradigms 9

2.1.1 Platform and Set-based Design 9

2.1.2 Modeling: Memory and Operations 14

2.2 System Architecture 18

2.2.1 Reference Machine and API 18

2.2.2 Communication Architecture Design 22

2.2.3 System Analysis 25

2.3 Low-power SoC Design 27

2.3.1 CMOS Circuit-level Low-power Design 27

2.3.2 Architecture-level Low-power Design 27

2.3.3 System-level Low-power Design 28

2.4 Network-on-Chip based SoC 28

2.4.1 Network-on-Chip Basics 29

2.4.2 NoC Design Considerations 41

2.4.3 Case Studies of Chip Implementation 48

3 Introduction to 3D Graphics 67

3.1 The 3D Graphics Pipeline 68

3.1.1 The Application Stage 68

3.1.2 The Geometry Stage 68

3.1.3 The Rendering Stage 74

3.2 Programmable 3D Graphics 78

3.2.1 Programmable Graphics Pipeline 78

3.2.2 Shader Models 81

4 Mobile 3D Graphics 85

4.1 Principles of Mobile 3D Graphics 85

4.1.1 Application Challenges 86

4.1.2 Design Principles 87

4.2 Mobile 3D Graphics APIs 91

4.2.1 KAIST MobileGL 91

4.2.2 Khronos OpenGL-ES 93

4.2.3 Microsoft's Direct3D-Mobile 95

4.3 Summary and Future Directions 96

5 Mobile 3D Graphics SoC 99

5.1 Low-power Rendering Processor 100

5.1.1 Early Depth Test 101

5.1.2 Logarithmic Datapaths 102

5.1.3 Low-power Texture Unit 104

5.1.4 Tile-based Rendering 106

5.1.5 Texture Compression 107

5.1.6 Texture Filtering and Anti-aliasing 109

5.2 Low-power Shader 110

5.2.1 Vertex Cache 110

5.2.2 Low-power Register File 111

5.2.3 Mobile Unified Shader 113

6 Real Chip Implementations 119

6.1 KAIST RAMP Architecture 119

6.1.1 Ramp-IV 120

6.1.2 Ramp-V 123

6.1.3 Ramp-VI 127

6.1.4 Ramp-VII 132

6.2 Industry Architecture 139

6.2.1 nVidia Mobile GPU - SC10 and Tegra 139

6.2.2 Sony PSP 143

6.2.3 Imagination Technology MBX/SGX 144

7 Low-power Rasterizer Design 149

7.1 Target System Architecture 149

7.2 Summary of Performance and Features 150

7.3 Block Diagram of the Rasterizer 150

7.4 Instruction Set Architecture (ISA) 151

7.5 Detailed Design with Register Transfer Level Code 154

7.5.1 Rasterization Top Block 154

7.5.2 Pipeline Architecture 156

7.5.3 Main Controller Design 156

7.5.4 Rasterization Core Unit 158

8 The Future of Mobile 3D Graphics 295

8.1 Game and Mapping Applications Involving Networking 295

8.2 Moves Towards More User-centered Applications 296

8.3 Final Remarks 297

Appendix Verilog HDL Design 299

A.1 Introduction to Verilog Design 299

A.2 Design Level 300

A.2.1 Behavior Level 300

A.2.2 Register Transfer Level 300

A.2.3 Gate Level 300

A.3 Design Flow 301

A.3.1 Specification 302

A.3.2 High-level Design 302

A.3.3 Low-level Design 303

A.3.4 RTL Coding 303

A.3.5 Simulation 304

A.3.6 Synthesis 304

A.3.7 Placement and Routing 305

A.4 Verilog Syntax 305

A.4.1 Modules 306

A.4.2 Logic Values and Numbers 307

A.4.3 Data Types 308

A.4.4 Operators 309

A.4.5 Assignment 311

A.4.6 Ports and Connections 312

A.4.7 Expressions 312

A.4.8 Instantiation 314

A.4.9 Miscellaneous 316

A.5 Example of Four-bit Adder with Zero Detection 318

A.6 Synthesis Scripts 320

Glossaries 323

Index 325