Monolithic Phase-Locked Loops and Clock Recovery Circuits: Theory and Design / Edition 1

Paperback (Print)
Buy New
Buy New from BN.com
$169.72
Used and New from Other Sellers
Used and New from Other Sellers
from $26.45
Usually ships in 1-2 business days
(Save 87%)
Other sellers (Paperback)
  • All (12) from $26.45   
  • New (7) from $174.07   
  • Used (5) from $26.45   

Overview

Featuring an extensive 40 page tutorial introduction, this carefully compiled anthology of 65 of the most important papers on phase-locked loops and clock recovery circuits brings you comprehensive coverage of the field-all in one self-contained volume. You'll gain an understanding of the analysis, design, simulation, and implementation of phase-locked loops and clock recovery circuits in CMOS and bipolar technologies along with valuable insights into the issues and trade-offs associated with phase locked systems for high speed, low power, and low noise.

Read More Show Less

Editorial Reviews

Booknews
A self-contained, unified reference containing reprints of articles organized to present a tutorial followed by chapters on the analysis, design, simulation, and implementation of PLLs and CRCs. These circuits find wide application in wireless and communication systems, disk drive electronics, high-speed digital circuits, and instrumentation. Annotation c. Book News, Inc., Portland, OR (booknews.com)
Read More Show Less

Product Details

  • ISBN-13: 9780780311497
  • Publisher: Wiley, John & Sons, Incorporated
  • Publication date: 4/18/1996
  • Edition description: New Edition
  • Edition number: 1
  • Pages: 508
  • Product dimensions: 8.66 (w) x 11.26 (h) x 1.23 (d)

Table of Contents

Preface.

Design of Monolithic Phase-Locked Loops and Clock Recovery Circuits—A Tutorial (B. Razavi).

BASIC THEORY.

Theory of AFC Synchronization (W. Gruen).

Color-Carrier Reference Phase Synchronization Accuracy in NTSC Color Television (D. Richman).

Charge-Pump Phase-Locked Loops (F. Gardner).

z-Domain Model for Discrete-Time PLLs (J. Hein & J. Scott).

Analyze PLLs with Discrete Time Modeling (J. Kovacs).

Properties of Frequency Difference Detectors (F. Gardner).

Frequency Detectors for PLL Acquisition in Timing and Carrier Recovery (D. Messerschmitt).

Analysis of Phase-Locked Timing Extraction Circuits for Pulse Code Transmission (E. Roza).

Optimization of Phase-Locked Loop Performance in Data Recovery Systems (R. Co & J. Mulligan).

Noise Properties of PLL Systems (V. Kroupa).

PLL/DLL System Noise Analysis for Low Jitter Clock Synthesizer Design (B. Kim, et al.).

Practical Approach Augurs PLL Noise in RF Synthesizers (M. O'Leary).

The Effects of Noise in Oscillators (E. Hafner).

A Simple Model of Feedback Oscillator Noise Spectrum (D. Leeson).

Noise in Relaxation Oscillators (A. Abidi & R. Meyer).

Analysis of Timing Jitter in CMOS Ring Oscillators (T. Weigandt, et al.).

Analysis, Modeling, and Simulation of Phase Noise in Monolithic Voltage-Controlled Oscillators (B. Razavi).

BUILDING BLOCKS.

Start-up and Frequency Stability in High-Frequency Oscillators (N. Nguyen & R. Meyer).

MOS Oscillators with Multi-Decade Tuning Range and Gigahertz Maximum Speed (M. Banu).

A Bipolar 1 GHz Multi-Decade Monolithic Variable-Frequency Oscillator (J. Wu).

A Digital Phase and Frequency Sensitive Detector (J. Brown).

A 3-State Phase Detector Can Improve Your Next PLL Design (C. Sharpe).

GaAs Monolithic Phase/Frequency Discriminator (I. Shahriary, et al.).

A New Phase-Locked Loop Timing Recovery Method for Digital Regenerators (J. Bellisio).

A Phase-Locked Loop with Digital Frequency Comparator for Timing Signal Recovery (J. Afonso, et al.).

Clock Recovery from Random Binary Signals (J. Alexander).

A Si Bipolar Phase and Frequency Detector IC for Clock Extraction up to 8 Gb/s (A. Pottbacker, et al.).

A Self-Correcting Clock Recovery Circuit (C. Hogge).

MODELING AND SIMULATION.

An Integrated PLL Clock Generator for 275 MHz Graphic Displays (G. Gutierrez & D. DeSimone).

The Macro Modeling of Phase-Locked Loopes for the SPICE Simulator (M. Sitkowski).

Modeling and Simulation of an Analog Charge Pump Phase-Locked Loop (S. Can & Y. Sahinkaya).

Mixed-Mode Simulation of Phase-Locked Loops (B. Antao, et al.).

Behavioral Representation for VCO and Detectors in Phase-Lock Systems (E. Liu & A. Sangiovanni-Vincentelli).

Behavioral Simulation Techniques for Phase/Delay-Locked Systems (A. Demir, et al.).

PHASE-LOCKED LOOPS.

A Monolithic Phase-Locked Loop with Detection Processor (E. Murthi).

A 200-MHz CMOS Phase-Locked Loop with Dual Phase Detectors (K. Ware, et al.).

High-Frequency Phase-Locked Loops in Monolithic Bipolar Technology (M. Soyuer & R. Meyer).

A 6-GHz Integrated Phase-Locked Loop Using AlGaAs/GaAs Heterojunction Bipolar Transistors (A. Buchwald, et al.).

A 6-GHz 60-mW BiCMOS Phase-Locked Loop with 2-V Supply (B. Razavi & J. Sung).

Design of PLL-Based Clock Generation Circuits (D. Jeong).

A Variable Delay Line PLL for CPU-Coprocessor Synchronization (M. Johnson & E. Hudson).

A PLL Clock Generator with 5 to 110 MHz of Lock Range for Microprocessors (I. Young, et al.).

A Wide-Bandwidth Low-Voltage PLL for PowerPC Microprocessors (J. Alvarez, et al.).

A 30-128 MHz Frequency Synthesizer Standard Cell (R. Bitting & W. Repasky).

Cell-Based Fully Integrated CMOS Frequency Synthesizers (D. Mijuskovic, et al.).

Fully-Integrated CMOS Phase-Locked Loop with 15 to 240 MHz Locking Range and -50 psec Jitter (I. Novof, et al.).

PLL Design for a 500 MB/s Interface (M. Horowitz, et al.).

CLOCK AND DATA RECOVERY CIRCUITS.

An Analog PLL-Based Clock and Data Recovery Circuit with High Input Jitter Tolerance (S. Sun).

A 30-MHz Hybrid Analog/Digital Clock Recovery Circuit in 2-μm CMOS (B. Kim, et al.).

A BiCMOS PLL-Based Data Separator Circuit with High Stability and Accuracy (S. Miyazawa, et al.).

A Versatile Clock Recovery Architecture and Monlithic Implementation (L. De Vito).

A 155-MHz Clock Recovery Delay- and Phase-Locked Loop (T. Lee & J. Bulzacchelli).

A Monolithic 156 Mb/s Clock and Data Recovery PLL Circuit using the Sample- and-Hold Technique (N. Ishihara & Y. Akazawa).

A Monolithic 480 Mb/s Parallel AGC/Decision/Clock Recovery Circuit in 1.2-μm CMOS (T. Hu & P. Gray).

A Monolithic 622 Mb/sec Clock Extraction and Data Retiming Circuit (B. Lai & R. Walker).

A 660 Mb/s CMOS Clock Recovery Circuit with Instantaneous Locking for NRZ Data and Burst-Mode Transmission (M. Banu & A. Dunlop).

A Monolithic 2.3-Gb/s 100-mW Clock and Data Recovery Circuit in Silicon Bipolar Technology (M. Soyuer).

A 50 MHz Phase- and Frequency-Locked Loop (R. Cordell, et al.).

NMOS ICs for Clock and Data Regeneration in Gigabit-per-Second Optical-Fiber Receivers (S. Enam & A. Abidi).

A PLL-Based 2.5-Gb/s Clock and Data Regenerator IC (H. Ransijn & P. O'Connor).

A 2.5-Gb/sec 15-mW BiCMOS Clock Recovery Circuit (B. Razavi & J. Sung).

An 8 GHz Silicon Bipolar Clock Recovery and Data Regenerator IC (A. Pottbacker & U. Langmann).

Author Index.

Subject Index.

Editor's Biography.

Read More Show Less

Customer Reviews

Be the first to write a review
( 0 )
Rating Distribution

5 Star

(0)

4 Star

(0)

3 Star

(0)

2 Star

(0)

1 Star

(0)

Your Rating:

Your Name: Create a Pen Name or

Barnes & Noble.com Review Rules

Our reader reviews allow you to share your comments on titles you liked, or didn't, with others. By submitting an online review, you are representing to Barnes & Noble.com that all information contained in your review is original and accurate in all respects, and that the submission of such content by you and the posting of such content by Barnes & Noble.com does not and will not violate the rights of any third party. Please follow the rules below to help ensure that your review can be posted.

Reviews by Our Customers Under the Age of 13

We highly value and respect everyone's opinion concerning the titles we offer. However, we cannot allow persons under the age of 13 to have accounts at BN.com or to post customer reviews. Please see our Terms of Use for more details.

What to exclude from your review:

Please do not write about reviews, commentary, or information posted on the product page. If you see any errors in the information on the product page, please send us an email.

Reviews should not contain any of the following:

  • - HTML tags, profanity, obscenities, vulgarities, or comments that defame anyone
  • - Time-sensitive information such as tour dates, signings, lectures, etc.
  • - Single-word reviews. Other people will read your review to discover why you liked or didn't like the title. Be descriptive.
  • - Comments focusing on the author or that may ruin the ending for others
  • - Phone numbers, addresses, URLs
  • - Pricing and availability information or alternative ordering information
  • - Advertisements or commercial solicitation

Reminder:

  • - By submitting a review, you grant to Barnes & Noble.com and its sublicensees the royalty-free, perpetual, irrevocable right and license to use the review in accordance with the Barnes & Noble.com Terms of Use.
  • - Barnes & Noble.com reserves the right not to post any review -- particularly those that do not follow the terms and conditions of these Rules. Barnes & Noble.com also reserves the right to remove any review at any time without notice.
  • - See Terms of Use for other conditions and disclaimers.
Search for Products You'd Like to Recommend

Recommend other products that relate to your review. Just search for them below and share!

Create a Pen Name

Your Pen Name is your unique identity on BN.com. It will appear on the reviews you write and other website activities. Your Pen Name cannot be edited, changed or deleted once submitted.

 
Your Pen Name can be any combination of alphanumeric characters (plus - and _), and must be at least two characters long.

Continue Anonymously

    If you find inappropriate content, please report it to Barnes & Noble
    Why is this product inappropriate?
    Comments (optional)