Multiple-Valued Logic: Proceedings of the 27th International Symposium on Multiple-Valued Logic, Antigonish, Nova Scotia, Canada, 1997

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Product Details

  • ISBN-13: 9780818679100
  • Publisher: IEEE Computer Society Press
  • Publication date: 5/28/1997
  • Pages: 300

Table of Contents

Message from the Symposium Chair
Message from the Program Co-Chairs
Chairs and Referees
Recent Developments in DNA-Computing 3
Decomposition of Multiple-Valued Relations 13
Finding Composition Trees for Multiple-Valued Functions 19
Functional Decomposition of MVL Functions Using Multi-Valued Decision Diagrams 27
Application of Resonant-Tunneling Quaternary Quantizer to Ultrahigh-Speed A/D Converter 35
Multiple-Junction Surface Tunnel Transistors for Multiple-Valued Logic Circuits 41
Enzyme Transistor Circuits for Biomolecular Computing 47
Comparison of the Worst and Best Sum-of-Products Expressions for Multiple-Valued Functions 55
Fast Algorithm for Minimizing Reed-Muller Expansions of Systems of Incompletely Specified MVL Functions 61
Sympathy-MV: Fast Exact Minimization of Fixed Polarity Multi-Valued Linear Expressions 66
Completeness Criteria in Set-Valued Logic Under Compositions with Union and Intersection 75
Hyperclones on a Finite Set 83
Set-Valued Functions and Regularity 89
Multiple-Valued Logic Minimization by Genetic Algorithms 97
Multiple-Valued Product-of-Sums Expression with Truncated Sum 103
Representation of Uncertain Belief Using Interval Probability 111
What Is Many-Valued Logic? 117
Family of Complex Hadamard Transforms: Relationship with Other Transforms and Complex Composite Spectra 125
Properties and Applications of Unified Complex Hadamard Transforms 131
Test Pattern Generation for Combinatorial Multi-Valued Networks Based on Generalized D-Algorithm 139
Fault Simulation in Sequential Multi-Valued Logic Networks 145
Many-Valuedness and Uncertainty 153
Multiple-Valued Programmable Logic Arrays with Universal Literals 163
VLSI Design of a Quaternary Multiplier with Direct Generation of Partial Products 169
One-Transistor-Cell 4-Valued Universal-Literal CAM for Cellular Logic Image Processing 175
On the Mutual Definability of Classes of Generalized Fuzzy Implications and of Classes of Generalized Negations and S-Norms 183
Training Fuzzy Logic Based Software Components for Reuse 189
Properties of Lindenmayer Fuzzy Languages and [alpha]-Driven Lindenmayer Languages 195
A Useful Application of CMOS Ternary Logic to the Realisation of Asynchronous Circuits 203
Design of Ternary CCD Circuits Referencing to Current-Mode CMOS Circuits 209
Quaternary Dynamic Differential Logic with Application to Fuzzy-Logic Circuits 215
A Proof Method for the Six-Valued Logic for Incomplete Information 223
Multiple-Valued Logic as a Programming Language 227
Multiple-Valued Immune Network Model and Its Simulations 233
Ternary Decision Diagrams: Survey 241
On the Synthesis of MVL Functions Using Input and Output Phase Assignments 253
Mixed Discrete Optimization of Multiple-Valued Systems 259
Design of an Asynchronous Digital System with B-Ternary Logic 265
Circuit Design from Kronecker Galois Field Decision Diagrams for Multiple-Valued Functions 275
Fourier Decision Diagrams on Finite Non-Abelian Groups with Preprocessing 281
Cube Diagram Bundles: A New Representation of Strongly Unspecified Multiple-Valued Functions and Relations 287
Author Index 293
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