Networks on Chip
As the number of processor cores and IP blocks integrated on a single chip is steadily growing, a systematic approach to design the communication infrastructure becomes necessary. Different variants of packed switched on-chip networks have been proposed by several groups during the past two years. This book summarizes the state of the art of these efforts and discusses the major issues from the physical integration to architecture to operating systems and application interfaces. It also provides a guideline and vision about the direction this field is moving to. Moreover, the book outlines the consequences of adopting design platforms based on packet switched network. The consequences may in fact be far reaching because many of the topics of distributed systems, distributed real-time systems, fault tolerant systems, parallel computer architecture, parallel programming as well as traditional system-on-chip issues will appear relevant but within the constraints of a single chip VLSI implementation.

1101005896
Networks on Chip
As the number of processor cores and IP blocks integrated on a single chip is steadily growing, a systematic approach to design the communication infrastructure becomes necessary. Different variants of packed switched on-chip networks have been proposed by several groups during the past two years. This book summarizes the state of the art of these efforts and discusses the major issues from the physical integration to architecture to operating systems and application interfaces. It also provides a guideline and vision about the direction this field is moving to. Moreover, the book outlines the consequences of adopting design platforms based on packet switched network. The consequences may in fact be far reaching because many of the topics of distributed systems, distributed real-time systems, fault tolerant systems, parallel computer architecture, parallel programming as well as traditional system-on-chip issues will appear relevant but within the constraints of a single chip VLSI implementation.

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Networks on Chip

Networks on Chip

Overview

As the number of processor cores and IP blocks integrated on a single chip is steadily growing, a systematic approach to design the communication infrastructure becomes necessary. Different variants of packed switched on-chip networks have been proposed by several groups during the past two years. This book summarizes the state of the art of these efforts and discusses the major issues from the physical integration to architecture to operating systems and application interfaces. It also provides a guideline and vision about the direction this field is moving to. Moreover, the book outlines the consequences of adopting design platforms based on packet switched network. The consequences may in fact be far reaching because many of the topics of distributed systems, distributed real-time systems, fault tolerant systems, parallel computer architecture, parallel programming as well as traditional system-on-chip issues will appear relevant but within the constraints of a single chip VLSI implementation.

Product Details

ISBN-13: 9781402073922
Publisher: Springer US
Publication date: 01/31/2003
Edition description: 2003
Pages: 303
Product dimensions: 6.10(w) x 9.25(h) x 0.03(d)

Table of Contents

System Design and Methodology.- Will Networks on Chip Close the Productivity Gap?.- A Design Methodology for NOC-Based Systems.- Mapping Concurrent Applications onto Architectural Platforms.- Guaranteeing the Quality of Services in Networks on Chip.- Hardware and Basic Infrastructure.- On Packet Switched Networks for On-Chip Communication.- Energy-Reliability trade-Off for NoCs.- Testing Strategies for Networks on Chip.- Clocking Strategies for Networks-on-Chip.- A Parallel Computer as a NOC Region.- An IP-Based On-Chip Packet-Switched Network.- Software and Application Interfaces.- Beyond the Von Neumann Machine.- NoC Application Programming Interfaces.- Multi-Level Software Validation for NoC.- Software for Multiprocessor Networks on Chip.
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