New Data Structures and Algorithms for Logic Synthesis and Verification

by Luca Gaetano Amaru

Overview

This book introduces new logic primitives for electronic design automation tools. The author approaches fundamental EDA problems from a different, unconventional perspective, in order to demonstrate the key role of rethinking EDA solutions in overcoming technological limitations of present and future technologies. The author discusses techniques that improve the efficiency of logic representation, manipulation and optimization tasks by taking advantage of majority and biconditional logic primitives. Readers will be enabled to accelerate formal methods by studying core properties of logic circuits and developing new frameworks for logic reasoning engines.

Product Details

ISBN-13:	9783319431734
Publisher:	Springer International Publishing
Publication date:	08/03/2016
Edition description:	1st ed. 2017
Pages:	156
Product dimensions:	6.10(w) x 9.25(h) x (d)

About the Author

Luca Gaetano Amaru is a Senior II, R&D Engineer at Synopsys Inc., Mountain View, CA. Formerly, he was a research assistant and PhD student in Computer Science at EPFL, Integrated Systems Laboratory, Lausanne, Switzerland, where he worked on new data structures and algorithms for logic synthesis and verification, under the direction of Prof. De Micheli, Dr. Gaillardon and Prof. Burg. He received his Bachelor's Degree in Electronic Engineering, with honors, from Politecnico di Torino, Italy, in 2009. In 2011 he received his double Master's Degree in Electronic Engineering, with honors, from Politecnico di Torino, Italy, and Politecnico di Milano, Italy. In 2014, he was a visiting researcher at Stanford University, Palo Alto, CA, USA.

Table of Contents

Introduction.- Part 1. Logic Representation, Manipulation and Optimization.- Biconditional Logic.- Majority Logic.- Part 2. Logic Satisfiability and Equivalence Checking.- Exploiting Logic Properties to Speedup SAT.- Majority Normal Form Representation and Satisfiability.- Improvements to the Equivalence Checking of Reversible Circuits.- Conclusions.