On-Chip Interconnect with aelite: Composable and Predictable Systems

by Andreas Hansson, Kees Goossens

Overview

The book provides a comprehensive description and implementation methodology for the Philips/NXP Aethereal/aelite Network-on-Chip (NoC). The presentation offers a systems perspective, starting from the system requirements and deriving and describing the resulting hardware architectures, embedded software, and accompanying design flow. Readers get an in depth view of the interconnect requirements, not centered only on performance and scalability, but also the multi-faceted, application-driven requirements, in particular composability and predictability. The book shows how these qualitative requirements are implemented in a state-of-the-art on-chip interconnect, and presents the realistic, quantitative costs.

Product Details

ISBN-13:	9781441964960
Publisher:	Springer New York
Publication date:	10/28/2010
Series:	Embedded Systems
Edition description:	2011
Pages:	210
Product dimensions:	6.10(w) x 9.25(h) x 0.24(d)

Table of Contents

1 Introduction 1

1.1 Trends 1

1.1.1 Application Requirements 1

1.1.2 Implementation and Design 3

1.1.3 Time and Cost 4

1.1.4 Summary 5

1.1.5 Example System 6

1.2 Requirements 9

1.2.1 Scalability 10

1.2.2 Diversity 10

1.2.3 Composability 11

1.2.4 Predictability 13

1.2.5 Reconfigurability 14

1.2.6 Automation 15

1.3 Key Components 16

1.4 Organisation 18

2 Proposed Solution 19

2.1 Architecture Overview 19

2.1.1 Contention-Free Routing 21

2.2 Scalability 22

2.2.1 Physical Scalability 23

2.2.2 Architectural Scalability 23

2.3 Diversity 24

2.3.1 Network Stack 25

2.3.2 Streaming Stack 25

2.3.3 Memory-Mapped Stack 26

2.4 Composability 28

2.4.1 Resource Flow-Control Scheme 28

2.4.2 Flow Control and Arbitration Granularities 29

2.4.3 Arbitration Unit Size 32

2.4.4 Temporal Interference 32

2.4.5 Summary 33

2.5 Predictability 33

2.5.1 Architecture Behaviour 34

2.5.2 Modelling and Analysis 34

2.6 Reconfigurability 35

2.6.1 Spatial and Temporal Granularity 35

2.6.2 Architectural Support 37

2.7 Automation 37

2.7.1 Input and Output 38

2.7.2 Division into Tools 38

2.8 Conclusions 39

3 Dimensioning 41

3.1 Local Buses 41

3.1.1 Target Bus 41

3.1.2 Initiator Bus 44

3.2 Atomisers 46

3.2.1 Limitations 47

3.3 Protocol Shells 47

3.3.1 Limitations 49

3.4 Clock Domain Crossings 49

3.5 Network Interfaces 50

3.5.1 Architecture 51

3.5.2 Experimental Results 54

3.5.3 Limitations 55

3.6 Routers 56

3.6.1 Experimental Results 58

3.6.2 Limitations 60

3.7 Mesochronous Links 60

3.7.1 Experimental Results 62

3.7.2 Limitations 62

3.8 Control Infrastructure 62

3.8.1 Unified Control and Data 63

3.8.2 Architectural Components 64

3.8.3 Limitations 67

3.9 Conclusions 67

4 Allocation 69

4.1 Sharing Slots 73

4.2 Problem Formulation 76

4.2.1 Application Specification 76

4.2.2 Network Topology Specification 79

4.2.3 Allocation Specification 81

4.2.4 Residual Resource Specification 82

4.3 Allocation Algorithm 84

4.3.1 Channel Traversal Order 85

4.3.2 Speculative Reservation 86

4.3.3 Path Selection 89

4.3.4 Refinement of Mapping 93

4.3.5 Slot Allocation 93

4.3.6 Resource Reservation 97

4.3.7 Limitations 98

4.4 Experimental Results 99

4.5 Conclusions 101

5 Instantiation 103

5.1 Hardware 104

5.1.1 SystemC Model 105

5.1.2 RTL Implementation 106

5.2 Allocations 107

5.3 Run-Time Library 108

5.3.1 Initialisation 109

5.3.2 Opening a Connection 111

5.3.3 Closing a Connection 113

5.3.4 Temporal Bounds 115

5.4 Experimental Results 115

5.4.1 Setup Time 116

5.4.2 Memory Requirements 117

5.4.3 Tear-Down Time 118

5.5 Conclusions 119

6 Verification 121

6.1 Problem Formulation 124

6.1.1 Cyclo-static Dataflow (CSDF) Graphs 125

6.1.2 Buffer Capacity Computation 127

6.2 Network Requirements 128

6.3 Network Behaviour 129

6.3.1 Slot Table Injection 129

6.3.2 Header Insertion 130

6.3.3 Path Latency 131

6.3.4 Return of Credits 131

6.4 Channel Model 132

6.4.1 Fixed Latency 132

6.4.2 Split Latency and Rate 134

6.4.3 Split Data and Credits 134

6.4.4 Final Model 134

6.4.5 Shell Model 135

6.5 Buffer Sizing 135

6.5.1 Modelling the Application 136

6.5.2 Synthetic Benchmarks 137

6.5.3 Mobile Phone SoC 139

6.5.4 Set-Top Box SoC 139

6.6 Conclusions 140

7 FPGA Case Study 143

7.1 Hardware Platform 144

7.1.1 Host Tile 145

7.1.2 Processor Tiles 146

7.2 Software Platform 147

7.2.1 Application Middleware 147

7.2.2 Design Flow 148

7.3 Application Mapping 149

7.4 Performance Verification 151

7.4.1 Soft Real-Time 151

7.4.2 Firm Real-Time 152

7.5 Conclusions 154

8 ASIC Case Study 157

8.1 Digital TV 157

8.1.1 Experimental Results 159

8.1.2 Scalability Analysis 162

8.2 Automotive Radio 165

8.2.1 Experimental Results 166

8.2.2 Scalability Analysis 167

8.3 Conclusions 168

9 Related Work 171

9.1 Scalability 171

9.1.1 Physical Scalability 171

9.1.2 Architectural Scalability 172

9.2 Diversity 173

9.3 Composability 174

9.3.1 Level of Composability 175

9.3.2 Enforcement Mechanism 175

9.3.3 Interference 176

9.4 Predictability 177

9.4.1 Enforcement Mechanism 177

9.4.2 Resource Allocation 177

9.4.3 Analysis Method 178

9.5 Reconfigurability 178

9.6 Automation 179

10 Conclusions and Future Work 181

10.1 Conclusions 181

10.2 Future Work 183

A Example Specification 185

A.1 Architecture 186

A.2 Communication 187

References 191

Glossary 201

Index 205