PCI Express System Architecture

PCI Express System Architecture

by Mindshare, Inc., Ravi Budruk, Don Anderson, Tom Shanley

ISBN-10: 0321156307

ISBN-13: 9780321156303

Pub. Date: 09/04/2003

Publisher: Addison-Wesley

PCI Express is the third-generation Peripheral Component Interconnect technology for a wide range of systems and peripheral devices. Incorporating recent advances in high-speed, point-to-point interconnects, PCI Express provides significantly higher performance, reliability, and enhanced capabilities -- at a lower cost -- than the previous PCI and PCI-X standards.


PCI Express is the third-generation Peripheral Component Interconnect technology for a wide range of systems and peripheral devices. Incorporating recent advances in high-speed, point-to-point interconnects, PCI Express provides significantly higher performance, reliability, and enhanced capabilities -- at a lower cost -- than the previous PCI and PCI-X standards. Therefore, anyone working on next-generation PC systems, BIOS and device driver development, and peripheral device design will need to have a thorough understanding of PCI Express.

PCI Express System Architecture provides an in-depth description and comprehensive reference to the PCI Express standard. The book contains information needed for design, verification, and test, as well as background information essential for writing low-level BIOS and device drivers. In addition, it offers valuable insight into the technology's evolution and cutting-edge features.

Following an overview of the PCI Express architecture, the book moves on to cover transaction protocols, the physical/electrical layer, power management, configuration, and more.

Product Details

Publication date:
PC System Architecture Series
Product dimensions:
7.37(w) x 9.25(h) x 2.12(d)

Table of Contents

About This Book
The MindShare Architecture Series1
Cautionary Note2
Intended Audience2
Prerequisite Knowledge3
Topics and Organization3
Documentation Conventions4
PCI Express4
Hexadecimal Notation4
Binary Notation4
Decimal Notation4
Bits Versus Bytes Notation5
Bit Fields5
Active Signal States5
Visit Our Web Site5
We Want Your Feedback6
Part 1The Big Picture
Chapter 1Architectural Perspective
Introduction To PCI Express9
Predecessor Buses Compared11
I/O Bus Architecture Perspective16
The PCI Express Way41
PCI Express Specifications54
Chapter 2Architecture Overview
Introduction to PCI Express Transactions55
PCI Express Device Layers69
Example of a Non-Posted Memory Read Transaction96
Hot Plug101
PCI Express Performance and Data Transfer Efficiency101
Part 2Transaction Protocol
Chapter 3Address Spaces & Transaction Routing
Two Types of Local Link Traffic108
Transaction Layer Packet Routing Basics113
Applying Routing Mechanisms121
Plug-And-Play Configuration of Routing Options135
Chapter 4Packet-Based Transactions
Introduction to the Packet-Based Protocol154
Transaction Layer Packets156
Data Link Layer Packets198
Chapter 5ACK/NAK Protocol
Reliable Transport of TLPs Across Each Link210
Elements of the ACK/NAK Protocol212
ACK/NAK DLLP Format219
ACK/NAK Protocol Details220
Error Situations Reliably Handled by ACK/NAK Protocol239
ACK/NAK Protocol Summary241
Recommended Priority To Schedule Packets244
Some More Examples244
Switch Cut-Through Mode248
Chapter 6QoS/TCs/VCs and Arbitration
Quality of Service252
Perspective on QOS/TC/VC and Arbitration255
Traffic Classes and Virtual Channels256
Chapter 7Flow Control
Flow Control Concept286
Flow Control Buffers288
Introduction to the Flow Control Mechanism290
Flow Control Packets293
Operation of the Flow Control Model - An Example294
Infinite Flow Control Advertisement301
The Minimum Flow Control Advertisement303
Flow Control Initialization304
Flow Control Updates Following FC_INIT308
Chapter 8Transaction Ordering
Producer/Consumer Model317
Native PCI Express Ordering Rules318
Relaxed Ordering319
Modified Ordering Rules Improve Performance322
Support for PCI Buses and Deadlock Avoidance326
Chapter 9Interrupts
Two Methods of Interrupt Delivery330
Message Signaled Interrupts331
Legacy PCI Interrupt Delivery342
Devices May Support Both MSI and Legacy Interrupts352
Special Consideration for Base System Peripherals353
Chapter 10Error Detection and Handling
Introduction to PCI Express Error Management356
Sources of PCI Express Errors361
Error Classifications368
How Errors are Reported370
Baseline Error Detection and Handling372
Advanced Error Reporting Mechanisms382
Summary of Error Logging and Reporting392
Part 3The Physical Layer
Chapter 11Physical Layer Logic
Physical Layer Overview397
Transmit Logic Details403
Receive Logic Details437
Physical Layer Error Handling450
Chapter 12Electrical Physical Layer
Electrical Physical Layer Overview453
High Speed Electrical Signaling455
LVDS Eye Diagram470
Transmitter Driver Characteristics477
Input Receiver Characteristics480
Electrical Physical Layer State in Power States481
Chapter 13System Reset
Two Categories of System Reset487
Reset Exit496
Link Wakeup from L2 Low Power State497
Chapter 14Link Initialization & Training
Link Initialization and Training Overview500
Ordered-Sets Used During Link Training and Initialization504
Link Training and Status State Machine (LTSSM)508
Detailed Description of LTSSM States513
LTSSM Related Configuration Registers549
Part 4Power-Related Topics
Chapter 15Power Budgeting
Introduction to Power Budgeting557
The Power Budgeting Elements558
Slot Power Limit Control562
The Power Budget Capabilities Register Set564
Chapter 16Power Management
Primer on Configuration Software569
Function Power Management585
Introduction to Link Power Management606
Link Active State Power Management608
Software Initiated Link Power Management629
Link Wake Protocol and PME Generation638
Part 5Optional Topics
Chapter 17Hot Plug
Hot Plug in the PCI Express Environment651
Elements Required to Support Hot Plug655
Card Removal and Insertion Procedures658
Standardized Usage Model663
Standard Hot Plug Controller Signaling Interface668
The Hot-Plug Controller Programming Interface670
Slot Numbering681
Quiescing Card and Driver681
The Primitives682
Chapter 18Add-in Cards and Connectors
Form Factors Under Development703
Part 6PCI Express Configuration
Chapter 19Configuration Overview
Definition of Device and Function712
Definition of Primary and Secondary Bus714
Topology Is Unknown At Startup714
Each Function Implements a Set of Configuration Registers715
Host/PCI Bridge's Configuration Registers716
Configuration Transactions Are Originated by the Processor718
Configuration Transactions Are Routed Via Bus, Device, and Function Number718
How a Function Is Discovered719
How To Differentiate a PCI-to-PCI Bridge From a Non-Bridge Function719
Chapter 20Configuration Mechanisms
PCI-Compatible Configuration Mechanism723
PCI Express Enhanced Configuration Mechanism731
Type 0 Configuration Request732
Type 1 Configuration Request733
Example PCI-Compatible Configuration Access735
Example Enhanced Configuration Access736
Initial Configuration Accesses738
Chapter 21PCI Express Enumeration
Enumerating a System With a Single Root Complex742
Enumerating a System With Multiple Root Complexes753
A Multifunction Device Within a Root Complex or a Switch758
An Endpoint Embedded in a Switch or Root Complex761
Memorize Your Identity763
Root Complex Register Blocks (RCRBs)765
Miscellaneous Rules766
Chapter 22PCI Compatible Configuration Registers
Header Type 0770
Header Type 1802
PCI-Compatible Capabilities845
Chapter 23Expansion ROMs
ROM Purpose--Device Can Be Used In Boot Process872
ROM Detection872
ROM Shadowing Required875
ROM Content875
Execution of Initialization Code885
Introduction to Open Firmware888
Chapter 24Express-Specific Configuration Registers
PCI Express Capability Register Set896
PCI Express Extended Capabilities929
Appendix ATest, Debug and Verification963
Appendix BMarkets & Applications for the PCI Express Architecture989
Appendix CImplementing Intelligent Adapters and Multi-Host Systems With PCI Express Technology999
Appendix DClass Codes1019
Appendix ELocked Transactions Series1033

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