PCI System Architecture / Edition 4

Paperback (Print)
Used and New from Other Sellers
Used and New from Other Sellers
from $1.99
Usually ships in 1-2 business days
(Save 97%)
Other sellers (Paperback)
  • All (20) from $1.99   
  • New (6) from $45.70   
  • Used (14) from $0.00   

Overview

PCI System Architecture is a detailed and comprehensive guide to the Peripheral Component Interconnect (PCI) Bus Specification, Intel's technology for fast communication between peripheral devices and the computer processor.

This new edition has been thoroughly updated, reorganized, and expanded to cover the PCI Local Bus Specification version 2.2 and other recent developments, including the new PCI Hot-Plug Specification, changes to the PCI-to-PCI Bridge Architecture Specification, revisions to the PCI Bus Power Management Interface Specification, and the new features of the PCI BIOS Specification.

This book provides clear and concise explanations of the relationship of PCI to the rest of the system and PCI fundamentals, including commands, read and write transfers, memory and I/O addressing, error handling, interrupts, and configuration transactions and registers. In addition, you will find specific information on such key topics as:

  • Hot-Plug Specification
  • Power management
  • CompactPCI
  • The 64-bit PCI Extension
  • 66 MHz PCI Implementation
  • Expansion ROMs
  • PCI-to-PCI Bridge and the PCI BIOS
  • Add-in cards and connectors
  • Bus arbitration
  • Reflected-wave switching
  • Early transaction end
  • Fast back-to-back and stepping

Changes from PCI 2.1 to PCI 2.2 and changes from PCI-to-PCI Bridge Specification 1.0 to 1.1 are visibly highlighted throughout the book so that those familiar with the previous versions can quickly get a handle on new features and functions.

Anyone who designs or tests hardware or software involving the PCI bus will find PCI System Architecture, Fourth Edition a valuable resource for understanding and working with this important technology.

The PC System Architecture Series is a crisply written and comprehensive set of guides to the most important PC hardware standards. Each title explains from a programmer's perspective the architecture, features, and operations of systems built using one particular type of chip or hardware specification.

Read More Show Less

Editorial Reviews

Booknews
A detailed guide to the Peripheral Component Interconnect (PCI) Bus Specification, Intel's technology for communication between peripheral devices and the computer processor. Explains the relationship of PCI to the rest of the system, and covers PCI fundamentals and changes between versions. This fourth edition has been expanded to cover the PCI Local Bus Specification version 2.2. For hardware and software design and support personnel familiar with PC and processor bus architecture. Shanley is an authority on PC system architecture. Anderson trains engineers, programmers, and technicians. Annotation c. Book News, Inc., Portland, OR (booknews.com)
Read More Show Less

Product Details

  • ISBN-13: 9780201309744
  • Publisher: Addison-Wesley
  • Publication date: 8/27/1999
  • Series: PC System Architecture Series
  • Edition description: REV
  • Edition number: 4
  • Pages: 832
  • Product dimensions: 7.40 (w) x 9.25 (h) x 1.63 (d)

Meet the Author

MindShare, Inc. is one of the leading technical training companies in the hardware industry, providing innovative courses for dozens of companies, including Intel, IBM, and Compaq.

Tom Shanley, president of MindShare, Inc., is one of the world's foremost authorities on computer system architecture. In the course of his career, he has trained thousands of engineers in hardware and software design.

Don Anderson is the author of many MindShare books. He passes on his wealth of experience in digital electronics and computer design by training engineers, programmers, and technicians for MindShare.

Read More Show Less

Read an Excerpt


Chapter 12: Early Transaction End

...Disconnect

Resumption of Disconnected Transaction Is Optional

Unlike a Retry, upon receipt of a Disconnect the master may or may not choose to rearbitrate for the bus and continue the transaction at the point of disconnection. As an example, a bridge might continue a memory read transaction past the first data phase to fill up a read-ahead buffer (i.e., a prefetch buffer) in case the originating master on the other side of the bridge wanted to read additional information. If the memory target that it's reading from disconnects from it at some point, the master would probably choose not to resume the transaction at the point of disconnection.

Reasons Target Issues Disconnect

Target Slow to Complete Subsequent Data Phase. Assume that the target determines that the latency to complete a data phase (except the first, which must adhere to the 16 clock rule) will be longer than eight PCI clocks. There are two cases:
CASE 1. The target determines that it can transfer the current data item within eight clocks and also knows that the master intends to perform another data phase (the master kept FRAME# asserted when it asserted IRDY#). The target has determined that it will not be able to transfer the next data item within eight clocks after entering the next data phase. The target must assert TRDY# and STOP# thereby forcing the master to disconnect from it upon completing the transfer of the current data item.

CASE 2. In this case, the target enters a data phase before determining that it cannot transfer a data item within eight clocks. The target must keep TRDY# deasserted and assert STOP# as soon as it determines that it cannot meet the eight clock rule. This forces the master to disconnect from the target without transferring the current data item.

It should be noted that this rule was added in revision 2.1 of the specification. The target used to be permitted to take as long as it needed to transfer a data item and would then issue a Disconnect A or B (i.e., a Disconnect With Data Transfer) to the initiator. In essence, the old wording of this rule permitted a target to tie up the bus for long periods of time. This rule ensures that a slow target will not tie up the bus for extended periods of time. This subject is covered in "Subsequent Data Phase Rule" on page 84.

Target Doesn't Support Burst Mode. If a target doesn't support burst mode and it detects that the master intends to perform a second data phase (FRAME# is still asserted when IRDY# is asserted), the target must force the master to disconnect from it. This can be handled in two ways:

METHOD 1. The target can assert TRDY# and STOP# in the first data phase, instructing the master to transfer the first data item and then disconnect. This method is preferred over the one below because it returns the bus to the idle state more quickly so another transaction can be initiated by the next bus owner.

METHOD 2. Alternately, the target could just assert TRDY# in the first data phase, thereby permitting the master to transfer the first data item and move into the second data phase. Upon entry into the second data phase, the target deasserts, TRDY# and asserts STOP#, instructing the master to disconnect without transferring the second data item.

Memory Target Doesn't Understand Addressing Sequence. If a memory target doesn't understand the addressing sequence (see "Memory Addressing" on page 143 for more information) indicated by the initiator via AD[1:01] during the address phase, the target must disconnect from the master. It has two options:

OPTION 1. The target can assert TRDY# and STOP# in the first data phase, instructing the master to transfer the first data item and then disconnect. This method is preferred over the one below because it returns the bus to the idle state more quickly so another transaction can be initiated by the next bus owner.

OPTION 2. Alternately, the target could just assert TRDY# in the first data phase, thereby permitting the master to transfer the first data item and move into the second data phase. Upon entry into the second data phase, the target deasserts TRDY# and asserts STOP#, instructing the master to disconnect without transferring the second data item.

This forces the initiator to fragment a burst transaction into single data phase transactions that the target can handle. The initiator may be using an AD[1:01] pattern defined in a later revision of the specification than the target was designed to.

Transfer Crosses Over Target's Address Boundary. If a target determines during the current data phase that the initiator intends to perform another data phase (FRAME# is still asserted) and that the current data item is the last within its address boundaries, the target must disconnect from the master. It has two options:

OPTION 1. The target can assert TRDY# and STOP# in the current data phase, instructing the master to transfer the current data item and then disconnect. This method is preferred over the one below because it returns the bus to the idle state more quickly so another transaction can be initiated by the next bus owner.

OPTION 2. Alternately, the target could just assert TRDY# in the current data phase, thereby permitting the master to transfer the first data item and move into the next data phase. Upon entry into the next data phase, the target deasserts TRDY# and asserts STOP#, instructing the master to disconnect without transferring the next data item.

The master then waits two PCI clocks and reasserts its REQ# to request ownership of the bus again. When it has re-acquired bus ownership, it resumes its transaction using the next dword address. This gives an opportunity to another target that implements the next sequential dword address to claim the transaction, thereby permitting the transfer to continue across target boundaries...

Read More Show Less

Table of Contents

About This Book.

1. Intro to PCI.

2. Intro to PCI Bus Operation.

3. Intro to Reflected-Wave Switching.

4. The Signal Groups.

5. PCI Bus Arbitration.

6. Master and Target Latency.

7. The Commands.

8. Read Transfers.

9. Write Transfers.

10. Memory and IO Addressing.

11. Fast Back-to-Back & Stepping.

12. Early Transaction End.

13. Error Detection and Handling.

14. Interrupts.

15. The 64-Bit PCI Extension.

16. 66MHz PCI Implementation.

17. Intro to Configuration Address Space.

18. Configuration Transactions.

19. Configuration Registers.

20. Expansion ROMs.

21. Add-in Cards and Connectors.

22. Hot-Plug PCI.

23. Power Management.

24. PCI-to-PCI Bridge.

25. Transaction Ordering & Deadlocks.

26. The PCI BIOS.
27. Locking.

28. CompactPCI and PMC.

Appendix: Glossary of Terms.

Read More Show Less

Customer Reviews

Be the first to write a review
( 0 )
Rating Distribution

5 Star

(0)

4 Star

(0)

3 Star

(0)

2 Star

(0)

1 Star

(0)

Your Rating:

Your Name: Create a Pen Name or

Barnes & Noble.com Review Rules

Our reader reviews allow you to share your comments on titles you liked, or didn't, with others. By submitting an online review, you are representing to Barnes & Noble.com that all information contained in your review is original and accurate in all respects, and that the submission of such content by you and the posting of such content by Barnes & Noble.com does not and will not violate the rights of any third party. Please follow the rules below to help ensure that your review can be posted.

Reviews by Our Customers Under the Age of 13

We highly value and respect everyone's opinion concerning the titles we offer. However, we cannot allow persons under the age of 13 to have accounts at BN.com or to post customer reviews. Please see our Terms of Use for more details.

What to exclude from your review:

Please do not write about reviews, commentary, or information posted on the product page. If you see any errors in the information on the product page, please send us an email.

Reviews should not contain any of the following:

  • - HTML tags, profanity, obscenities, vulgarities, or comments that defame anyone
  • - Time-sensitive information such as tour dates, signings, lectures, etc.
  • - Single-word reviews. Other people will read your review to discover why you liked or didn't like the title. Be descriptive.
  • - Comments focusing on the author or that may ruin the ending for others
  • - Phone numbers, addresses, URLs
  • - Pricing and availability information or alternative ordering information
  • - Advertisements or commercial solicitation

Reminder:

  • - By submitting a review, you grant to Barnes & Noble.com and its sublicensees the royalty-free, perpetual, irrevocable right and license to use the review in accordance with the Barnes & Noble.com Terms of Use.
  • - Barnes & Noble.com reserves the right not to post any review -- particularly those that do not follow the terms and conditions of these Rules. Barnes & Noble.com also reserves the right to remove any review at any time without notice.
  • - See Terms of Use for other conditions and disclaimers.
Search for Products You'd Like to Recommend

Recommend other products that relate to your review. Just search for them below and share!

Create a Pen Name

Your Pen Name is your unique identity on BN.com. It will appear on the reviews you write and other website activities. Your Pen Name cannot be edited, changed or deleted once submitted.

 
Your Pen Name can be any combination of alphanumeric characters (plus - and _), and must be at least two characters long.

Continue Anonymously

    If you find inappropriate content, please report it to Barnes & Noble
    Why is this product inappropriate?
    Comments (optional)